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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=XUmWALNl; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="XUmWALNl" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 9AA2E752; Wed, 18 Jun 2025 12:05:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1750241126; bh=7lEyNd9xMrZh0TKqLkR27JbjLcGIiTLH3RfkijHETvE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=XUmWALNlWm9GbOz9gEfwRGyCCs3tny7AQZvy4VaPg5iN4I09fbswyLPVteeh4wUrU Lu9ggWN6XStTAqSI7sVaSKJtbN8wJmEsH9jdRDUP1FHqMvG1tDW4ksUkUCSgeoNoqs d0QMkObTxrmzfaLKs8gbdXlXwOHbh48Cym1VVwHw= Message-ID: <357d8e74-eb6c-48d0-b9cc-eab4ed26904d@ideasonboard.com> Date: Wed, 18 Jun 2025 13:05:35 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 3/4] drm/atomic-helper: Re-order bridge chain pre-enable and post-disable To: Marek Szyprowski , Maxime Ripard Cc: Aradhya Bhatia , DRI Development List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Devarsh Thakkar , Jayesh Choudhary , Alexander Sverdlin , Dmitry Baryshkov , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter References: <20250605171524.27222-1-aradhya.bhatia@linux.dev> <20250605171524.27222-4-aradhya.bhatia@linux.dev> <2c51cf39-13cb-413f-8dd5-53bc1c11467a@samsung.com> <306f142f-f9c9-44ab-a5b9-c71db76b2b80@ideasonboard.com> <3adb1d12-7cd5-4beb-9978-c3cae702f338@ideasonboard.com> <20250618-silent-oriole-of-fertility-3cbbd6@houat> <3c5d43a2-fdbe-4cbe-bf45-09bfcb18dcb3@samsung.com> Content-Language: en-US From: Tomi Valkeinen Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8 Content-Transfer-Encoding: 8bit Hi, On 18/06/2025 13:01, Marek Szyprowski wrote: > On 18.06.2025 10:27, Maxime Ripard wrote: >> On Wed, Jun 18, 2025 at 08:30:39AM +0200, Marek Szyprowski wrote: >>> On 16.06.2025 17:40, Tomi Valkeinen wrote: >>>> On 12/06/2025 09:31, Marek Szyprowski wrote: >>>>> On 12.06.2025 07:49, Tomi Valkeinen wrote: >>>>>> On 11/06/2025 13:45, Marek Szyprowski wrote: >>>>>>> On 05.06.2025 19:15, Aradhya Bhatia wrote: >>>>>>>> From: Aradhya Bhatia >>>>>>>> >>>>>>>> Move the bridge pre_enable call before crtc enable, and the bridge >>>>>>>> post_disable call after the crtc disable. >>>>>>>> >>>>>>>> The sequence of enable after this patch will look like: >>>>>>>> >>>>>>>> bridge[n]_pre_enable >>>>>>>> ... >>>>>>>> bridge[1]_pre_enable >>>>>>>> >>>>>>>> crtc_enable >>>>>>>> encoder_enable >>>>>>>> >>>>>>>> bridge[1]_enable >>>>>>>> ... >>>>>>>> bridge[n]_enable >>>>>>>> >>>>>>>> And, the disable sequence for the display pipeline will look like: >>>>>>>> >>>>>>>> bridge[n]_disable >>>>>>>> ... >>>>>>>> bridge[1]_disable >>>>>>>> >>>>>>>> encoder_disable >>>>>>>> crtc_disable >>>>>>>> >>>>>>>> bridge[1]_post_disable >>>>>>>> ... >>>>>>>> bridge[n]_post_disable >>>>>>>> >>>>>>>> The definition of bridge pre_enable hook says that, >>>>>>>> "The display pipe (i.e. clocks and timing signals) feeding this bridge >>>>>>>> will not yet be running when this callback is called". >>>>>>>> >>>>>>>> Since CRTC is also a source feeding the bridge, it should not be enabled >>>>>>>> before the bridges in the pipeline are pre_enabled. Fix that by >>>>>>>> re-ordering the sequence of bridge pre_enable and bridge post_disable. >>>>>>>> >>>>>>>> While at it, update the drm bridge API documentation as well. >>>>>>>> >>>>>>>> Acked-by: Dmitry Baryshkov >>>>>>>> Reviewed-by: Tomi Valkeinen >>>>>>>> Reviewed-by: Thomas Zimmermann >>>>>>>> Tested-by: Tomi Valkeinen >>>>>>>> Tested-by: Alexander Sverdlin >>>>>>>> Signed-off-by: Aradhya Bhatia >>>>>>>> Signed-off-by: Aradhya Bhatia >>>>>>> This patch landed in today's linux-next as commit c9b1150a68d9 >>>>>>> ("drm/atomic-helper: Re-order bridge chain pre-enable and >>>>>>> post-disable"). In my tests I found that it breaks booting of Samsung >>>>>>> Exynos 5420/5800 based Chromebooks (Peach-Pit and Peach-Pi). Both of >>>>>>> them use Exynos DRM with Exynos_DP sub-driver (Analogix DP) and EDP >>>>>>> panel. Booting stops at '[drm] Initialized exynos 1.1.0 for exynos-drm >>>>>>> on minor 0' message. On the other hand, the Samsung Exynos5250 based >>>>>>> Snow Chromebook boots fine, but it uses dp-lvds nxp,ptn3460 bridge and >>>>>>> lvds panel instead of edp panels. This looks like some sort of deadlock, >>>>>>> because if I disable FBDEV emulation, those boards boots fine and I'm >>>>>>> able to run modetest and enable the display. Also the DRM kernel logger >>>>>>> seems to be working fine, although I didn't check the screen output yet, >>>>>>> as I only have a remote access to those boards. I will investigate it >>>>>>> further and let You know. >>>>>> Thanks for the report. I was trying to understand the pipeline, but I'm >>>>>> a bit confused. Above you say Peach-Pit uses DP and EDP panel, but if I >>>>>> look at arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts, it connects >>>>>> a dp->lvds bridge (parade,ps8625). Peach-Pi seems to connect to an eDP >>>>>> panel. >>>>>> >>>>>> Is the above correct? Do both Peach-Pi and Peach-Pit fail? >>>>> Yes, sorry, my fault. I much have checked the same (peach-pi) dts 2 >>>>> times. Both Peach-Pi and Peach-Pit fails, while Snow works fine. All >>>>> three use the same Exynos DP (based on analogix dp) driver. I will try >>>>> to play a bit more with those boards in the afternoon, hopefully getting >>>>> some more hints where the issue is. >>>> Did you get a chance to test this more? Any hints what happens will help =) >>> I've spent some time debugging this issue, but so far I only got >>> something I don't really understand. This issue is somehow related with >>> the DP clock enabling and disabling, what is being done from >>> exynos_dp_poweron() and exynos_dp_poweroff() functions, which are called >>> from analogix_dp_resume() and analogix_dp_suspend(). The lockup happens >>> somewhere while registering the fbdev console, with console lock held, >>> what makes debugging much harder. >> You can skip the locking part with the fb.lockless_register_fb=1 kernel >> parameter. It's of course not meant for anything but debugging, but it's >> useful :) > > I've finally found where is the problem! It turned out that the issue is > in the exynos_drm_fimd driver, in the code for enabling the display port > clock (fimd_dp_clock_enable() >  function). It touches FIMD regs, but it was not guarded with FIMD's > runtime pm calls and after the $subject change it happened that > exynos_dp/analogix_dp code called the clock enable/disable when FIMD > driver (which implements the CRTC object) was not runtime resumed. > Previously all dp clock handling was done when CRTC was enabled, thus > the FIMD device was in the resumed runtime pm state. > > I will send a patch fixing this soon. Alright, sounds like we don't need to revert the re-ordering patch after all =). Thanks for debugging this. Tomi