Re: [PATCH net-next v3 3/8] dt-bindings: net: dsa: Add SoC-e SWIP switch

[Vasilij Strassheim <v.strassheim@linutronix.de>]

On Wed, 2026-10-07 at 15:54 -0500, Rob Herring wrote:
> On Wed, Sep 23, 2026 at 12:39:30PM +0200, Vasilij Strassheim wrote:
> > Add a binding for SoC-e FPGA-based Ethernet switch IP cores.
> > 
> > The compatible identifies a register layout characterized by the core
> > and feature identification registers at the encoded offsets. The
> > concrete synthesis-time configuration is then autodetected from these
> > registers.
> > 
> > Describe the Ethernet ports and the optional integrated MDIO controller
> > with its generic MMIO mux and child buses.
> > 
> > Signed-off-by: Vasilij Strassheim <v.strassheim@linutronix.de>
> > ---
> >  .../devicetree/bindings/net/dsa/soce,swip.yaml     | 162 +++++++++++++++++++++
> >  1 file changed, 162 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/dsa/soce,swip.yaml b/Documentation/devicetree/bindings/net/dsa/soce,swip.yaml
> > new file mode 100644
> > index 000000000000..d614fb2a29d3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/dsa/soce,swip.yaml
> > @@ -0,0 +1,162 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/dsa/soce,swip.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SoC-e ethernet switch IP core for FPGAs
> > +
> > +maintainers:
> > +  - Vasilij Strassheim <v.strassheim@linutronix.de>
> > +
> > +description:
> > +  SoC-e Ethernet switch IP cores are FPGA-based switches whose features
> > +  and number of ports are selected at synthesis time. Ports can connect
> > +  to CPUs, external PHYs, FPGA logic, or other switch cores. An integrated
> > +  MDIO controller accesses the per-port external buses through a mux.
> > +
> > +$ref: dsa.yaml#
> 
> Doesn't look like you use any DSA properties. Can you use 
> ethernet-switch.yaml instead. Also, if you don't have any custom 
> properties, you need to ref "dsa.yaml#/$defs/ethernet-ports" instead.

Yes, I will use dsa.yaml#/$defs/ethernet-ports.
This will also make the local dsa-port.yaml reference and
unevaluatedProperties: false redundant, so I will fix this as well.

> 
> > +
> > +properties:
> > +  compatible:
> > +    const: soce,swip-00-04-0c-10
> > +    description:
> > +      Register layout with the core version register at offset 0x00 and
> > +      feature identification registers at offsets 0x04, 0x0c, and 0x10.
> 
> Do you expect these to change? Kind of an odd compatible, but okay...

No, I don't expect them to change. But since this is FPGA IP which is
easy to be changed, I would not rely on them either.
Anyway, I haven't found a better solution yet. MV88E6xxx has a similar
approach. More generic compatible is not a viable option.


Thanks,
Vasilij