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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc1beae6484sm1288684a12.4.2026.08.26.10.38.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Aug 2026 10:38:45 -0700 (PDT) Message-ID: <35c1a38c-c174-455d-ba16-ecba1f7990ba@oss.qualcomm.com> Date: Wed, 26 Aug 2026 23:08:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 11/12] arm_mpam: change MPAM-Fb error IRQ to use a threaded IRQ handler To: Andre Przywara , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , Ritwick Sharma , Gavin Shan , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260807105451.3728284-1-andre.przywara@arm.com> <20260807105451.3728284-12-andre.przywara@arm.com> Content-Language: en-US From: Srivathsa L Rao In-Reply-To: <20260807105451.3728284-12-andre.przywara@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=EMA2FVZC c=1 sm=1 tr=0 ts=6a8f24a7 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=ChElBHoWxOA9GRTPlqMA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: Byi8BmCHhon7xVljNXrgHGQttJelStDt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDE0NyBTYWx0ZWRfX3V61dp5CrtlX 7SxMDD5ndI0c3I/k7IH3pRsvw/ibEDbANJ1r4gnvg9hUvOiKYDWU+pDrW28g3tnaj0yv8hnZMsm PhjKitKtpE+WuuoVl7pNqi+vvkMzQMD3PF3dzfMXWspXmGBB8Gm0cANQqHRBCfgUXeqv+rPgEt4 5SV41wtAUfG2hLMRAhvJMUTK+VOl+gy/AGK7iPytyaeL/BNgmmTZyOEnigRrpup26kY3MKgXYv2 VlwAEiN7N1Fo7RPtF0itNanovJsxRQwEcJ8a4OK+fzYsWcrqaVPX28vTMdJY6HAPDDKihJjuvQ+ Pwzm3wl/DzujQQy/aB8XHk3JELXYwHMBFuZtMymmtHfF63nvXjKHAv0XHv0p2BfZUBk9ZUCbT4r B7+VtX1vFWqHNXhRGoPLq0fbhj6+F1JPuttwgHdj79AuWi/wbka0D5KYjPhFgF0YVbRoBFt07Iv 6SCqGR1zrvE5zrwCUxQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDE0NyBTYWx0ZWRfXzmUhap2NazPD o3eZIjEU+yY5SzLMGdT/vnGULQC+YOGqPJLR09z8fK4o0phJZvaTcsKBbzoZvdUagufMSOmMUU8 3p2vY9O9aoXWcSaH2l3jnBwIRDazcGs= X-Proofpoint-GUID: Byi8BmCHhon7xVljNXrgHGQttJelStDt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-26_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260147 On 8/7/2026 4:24 PM, Andre Przywara wrote: > When an MPAM MSC gets into an error condition, it can trigger an error > IRQ. We cannot really do much about those errors, but we at least query > and log the error, then disable MPAM functionality. > > This error report relies on reading the MSC's error status register > (ESR) in the current hard-IRQ handler, which is not possible for MPAM-Fb > based MSC accesses, since they involve mailbox routines that might sleep. > The same is true for clearing the interrupt at the source, which requires > a (potentially sleeping) MSC access as well. > > Change the error IRQ handler to be a threaded interrupt, but keep the > handling in the hard-IRQ part for MMIO MSCs. This is needed since the > CPU affinity check in the MSC accessors requires a non-preemptible > context. > When the MSC is using an MPAM-Fb based access, we push the work into the > threaded part of the handler, where the accessors are allowed to sleep. > Also forbid per-CPU interrupts (PPIs) for MPAM-Fb, as we cannot use a > threaded IRQ here. > > The actual IRQ handler learns how to deal with errors. We cannot really > handle them, but we can try our best to disable the IRQ anyway. > Should the level IRQ line deactivation fail on the device side, we mask > the IRQ on the irqchip level, to prevent an interrupt storm. > > Signed-off-by: Andre Przywara > --- > drivers/resctrl/mpam_devices.c | 77 ++++++++++++++++++++++++++++------ > 1 file changed, 65 insertions(+), 12 deletions(-) > > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c > index fb2fba5ba96d..4b1382fce2be 100644 > --- a/drivers/resctrl/mpam_devices.c > +++ b/drivers/resctrl/mpam_devices.c Reviewed-by: Srivathsa L Rao