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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=H+DrBeYi c=1 sm=1 tr=0 ts=6a27d662 cx=c_pps a=wuOIiItHwq1biOnFUQQHKA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=f2xlcQsDh-InlZPZBw4A:9 a=QEXdDO2ut3YA:10 a=XD7yVLdPMpWraOa8Un9W:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDA4MyBTYWx0ZWRfX6lM5JnVlElii ips/6gSsWZRmzjcBkdFGBVvTaN5jSE7zA8SEZRKfoHIZzQhMem+mhbBk86S1A/0RkiBnSsB0En4 IXZK6iVxUIh/SRXQeToYQdVzduxCg6axGteA5VhwtSLXzzJaRfyp1m2y44GmzfGI/GvRWlM7ict 6En3UstZ4mHhQZu51gj2LmmQ9CwMfQETo3wHREWgVIz7xGnDr781OmMxWgQOXyMOs9G7oBLhzuu EzOI8NgdvdK5OcO0+ghCpTD6h7W/zI18ZknjjLohgIJZu3nwwTpBdJ8YCJBy4tvw8QvtByN7hrd /my5qmpoCgRzHkN9I7td46Y7QyQrgsacXI6Z1FVnIj19QPVD2/5oLkdO2VzOf+oIxrTAO7Ua/wE WI9Fh/TZ19h+hvbOJ6TjeyPi2bp7rnFfLoae3UAb5u1O8MhA0IuSLgADNYHxXDfV/gE1ZUTi/lG UFSLmaGBCCpYnj6y5CA== X-Proofpoint-ORIG-GUID: 2Cvn6FCUTTmyDAvKnyUv2P5n8Lt8Q0b9 X-Proofpoint-GUID: 2Cvn6FCUTTmyDAvKnyUv2P5n8Lt8Q0b9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_02,2026-06-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090083 On 6/9/26 10:55 AM, Konrad Dybcio wrote: > On 6/9/26 10:10 AM, Stephan Gerhold wrote: >> On Tue, Jun 09, 2026 at 09:52:51AM +0200, Miquel Raynal wrote: >>>>> On MDM9607, there is only a single controllable clock for the NAND >>>>> controller (RPM_SMD_QPIC_CLK). The same situation also applies e.g. for >>>>> qcom,sdx55-nand, but the corresponding device tree (qcom-sdx55.dtsi) works >>>>> around that by assigning a dummy clock (&nand_clk_dummy) to the second >>>>> clock ("aon") that is required by the dt-bindings. This is not really >>>>> useful, so avoid doing that for new platforms by excluding the second "aon" >>>>> clock entry in the dt-bindings. >>>> >>>> Reviewed-by: Krzysztof Kozlowski >>> >>> What is the problem in giving twice the same clock? If this is what is >>> done in the hardware routing, I do not see the reason for more >>> complexity in the binding? >>> >> >> I had that in my first draft for this series, but this would be wrong >> IMO. I suspect there is no QPIC/NAND related "aon" (always-on) clock on >> this platform at all. I'm not sure about MDM9607 in particular (maybe >> someone from Qualcomm can confirm), but a similar platform I was looking >> into at some point actually had *3* separate clocks for QPIC in the >> hardware and none of them were called "aon" ... > > gcc_qpic_ahb_clk (50/100/133.(3) MHz sourced from PCNoC_bfdcd_clk_src) > gcc_qpic_clk (likewise, sourced from qpic_clk_src which is sourced > from GPLLs) > gcc_qpic_system_clk (32 KHz) > > No clock containing the substring 'aon' in its name on this platform Looking at SDX65, perhaps the 32 Khz clock is the "aon" one after all.. The NAND documentation says CC_QPIC_SYSTEM_CLK - Always-on timeout clock (32 KHz) Konrad