From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751743AbeAYLff (ORCPT ); Thu, 25 Jan 2018 06:35:35 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:63302 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751409AbeAYLfe (ORCPT ); Thu, 25 Jan 2018 06:35:34 -0500 From: Philippe CORNU To: Brian Norris CC: Archit Taneja , Andrzej Hajda , Laurent Pinchart , David Airlie , Benjamin Gaignard , Bhumika Goyal , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , Sandy Huang , Heiko Stubner , "linux-arm-kernel@lists.infradead.org" , "linux-rockchip@lists.infradead.org" , Yannick FERTRE , Vincent ABRIOU , Alexandre TORGUE , Maxime Coquelin , Ludovic BARRE , Mickael REULIER , "hl@rock-chips.com" , "Chris Zhong" , "nickey.yang@rock-chips.com" Subject: Re: [PATCH v3] drm/bridge/synopsys: dsi: add optional pixel clock Thread-Topic: [PATCH v3] drm/bridge/synopsys: dsi: add optional pixel clock Thread-Index: AQHTlGzLGXXRIzYyCUCpCWgoURDUQKOB3cMAgADSxwCAAJKqAIABJDMA Date: Thu, 25 Jan 2018 11:34:51 +0000 Message-ID: <35d72e79-7200-dec7-2b53-a672f1c02b3b@st.com> References: <20180123170806.5282-1-philippe.cornu@st.com> <20180123204939.qirvr34mlwgiwmqz@ban.mtv.corp.google.com> <507552a3-c68f-d6ac-a747-b8f5168d0d41@st.com> <20180124180859.mr736rpzysq5vn54@ban.mtv.corp.google.com> In-Reply-To: <20180124180859.mr736rpzysq5vn54@ban.mtv.corp.google.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] Content-Type: text/plain; charset="utf-8" Content-ID: <38BA446193370D47BDBB66B8E2EE22D5@st.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-01-25_03:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w0PBZdBB020040 Hi Brian, On 01/24/2018 07:09 PM, Brian Norris wrote: > On Wed, Jan 24, 2018 at 09:24:06AM +0000, Philippe CORNU wrote: >> On 01/23/2018 09:49 PM, Brian Norris wrote: >>> On Tue, Jan 23, 2018 at 06:08:06PM +0100, Philippe Cornu wrote: >>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c >>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > >>>> @@ -828,6 +833,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev, >>>> return ERR_PTR(ret); >>>> } >>>> >>>> + dsi->px_clk = devm_clk_get(dev, "px_clk"); >>> >>> Did you write a device tree binding document update for this anywhere? >> >> Many thanks for your review, >> >> yes, "px_clk" is already documented, please have a look to >> Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt > > Ah, I see. Normally I expect that the binding document is sent around > when the first user of it shows up, but I guess that's not a > requirement. Sorry I missed that! > > Just a note: I don't think that Rockchip systems have an equivalent > clock from which to directly derive the pixel clock rate. I believe it's > controlled through additional dividers that are not part of the common > clock framework. So this isn't particularly useful for them. > > I don't think it's worth very much in this case, but: > > Reviewed-by: Brian Norris > Many thanks for the review and your comments. Looking more deeply into the rockchip vop driver (in order to understand how the px clock is used), I can see that adjusted_mode/mode_fixup is (now) used. I have already tried to use adjusted_mode/mode_fixup on stm32 but without success. Nevertheless, I will do more tests with adjusted_mode/mode_fixup as it could help to have a simpler patch than adding the px_clk. Many thanks, Philippe :-)