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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amlogic.com; Received: from KL1PR03MB5778.apcprd03.prod.outlook.com (2603:1096:820:6d::13) by TYZPR03MB6893.apcprd03.prod.outlook.com (2603:1096:400:286::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.10; Fri, 6 Nov 2026 03:16:29 +0000 Received: from KL1PR03MB5778.apcprd03.prod.outlook.com ([fe80::e1e:5c95:a889:828e]) by KL1PR03MB5778.apcprd03.prod.outlook.com ([fe80::e1e:5c95:a889:828e%4]) with mapi id 15.21.0569.011; Fri, 6 Nov 2026 03:16:29 +0000 Message-ID: <35dc1ebf-5194-4ec8-adfb-dcc8ea717750@amlogic.com> Date: Fri, 6 Nov 2026 11:16:21 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/7] dt-bindings: net: amlogic,meson-dwmac: add amlogic,t7-dwmac To: Krzysztof Kozlowski , Lucas Tanure Cc: xianwei.zhao@amlogic.com, Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: <20261103163715.385394-1-tanure@linux.com> <20261103163715.385394-3-tanure@linux.com> <20261105-stoic-cricket-of-tolerance-cb3014@quoll> From: Chuan Liu In-Reply-To: <20261105-stoic-cricket-of-tolerance-cb3014@quoll> Content-Type: text/plain; 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Without it, the controller cannot >> + complete DMA transfers. >> + - description: >> + clock of the register block holding PRG_ETH0 and PRG_ETH1. >> + Without it, the block reads as zero and ignores writes. > > This sounds like you take clock from other block. That's wrong, that > device should take its own clock. I see that the clock in the dts patch corresponds to <&clkc_periphs CLKID_SYS_ETHPHY>. This clock provides the working clock for the APB Bus of the ETH PHY controller, and this clock will affect the register reading and writing of the ETH PHY (including the ETH_PLL). See section 15.3.4.2 RegisterDescription in A311D2 Datasheet for details. > > >> + >> + clock-names: >> + items: >> + - const: stmmaceth >> + - const: clkin0 >> + - const: clkin1 >> + - const: pipeline >> + - const: pclk >> + >> + # The PHY adds the 2ns RGMII delays, see ethernet-controller.yaml. >> + # The RX delay line of this glue is fine tuning in 200ps steps, >> + # added on top of what phy-mode describes. The TX side has no fine >> + # tuning: its only step is a quarter of the clock period, the full >> + # 2ns at 1Gbit/s, so the TX property is not accepted. >> + tx-internal-delay-ps: false >> + >> + # Deprecated: new SoCs use the standard *-internal-delay-ps >> + # properties instead. >> + amlogic,tx-delay-ns: false >> + amlogic,rx-delay-ns: false >> + >> + # Delay definitions for Meson8b and newer >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - amlogic,meson8b-dwmac >> + - amlogic,meson8m2-dwmac >> + - amlogic,meson-gxbb-dwmac >> + - amlogic,meson-axg-dwmac >> + - amlogic,meson-g12a-dwmac >> + then: >> + properties: >> amlogic,tx-delay-ns: >> enum: [0, 2, 4, 6] >> default: 2 >> @@ -106,6 +160,7 @@ allOf: >> contains: >> enum: >> - amlogic,meson-g12a-dwmac >> + - amlogic,t7-dwmac >> then: >> properties: >> rx-internal-delay-ps: >> @@ -142,6 +197,10 @@ properties: >> - items: >> - const: amlogic,meson6-dwmac >> - const: snps,dwmac >> + - items: >> + - const: amlogic,t7-dwmac >> + - const: snps,dwmac-5.10a >> + - const: snps,dwmac > > I see no such hunk in the code, so not sure how to review this. > > Best regards, > Krzysztof > > > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic -- Best regards, Chuan