From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: <agross@kernel.org>, <lgirdwood@gmail.com>, <broonie@kernel.org>,
<robh+dt@kernel.org>, <quic_plai@quicinc.com>,
<bgoswami@codeaurora.org>, <perex@perex.cz>, <tiwai@suse.com>,
<srinivas.kandagatla@linaro.org>, <rohitkr@codeaurora.org>,
<linux-arm-msm@vger.kernel.org>, <alsa-devel@alsa-project.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<swboyd@chromium.org>, <judyhsiao@chromium.org>,
Linus Walleij <linus.walleij@linaro.org>,
<linux-gpio@vger.kernel.org>,
Venkata Prasad Potturu <quic_potturu@quicinc.com>
Subject: Re: [PATCH v10 4/7] pinctrl: qcom: Update lpi pin group structure
Date: Tue, 15 Mar 2022 20:46:11 +0530 [thread overview]
Message-ID: <35e43f3a-8d48-5c2a-b5f6-9220cead7ff0@quicinc.com> (raw)
In-Reply-To: <YieYr00MRUfeSE1B@ripper>
On 3/8/2022 11:25 PM, Bjorn Andersson wrote:
Thanks for Your Time Bjorn!!!
> On Tue 08 Mar 03:03 PST 2022, Srinivasa Rao Mandadapu wrote:
>
>> Update lpi group structure with core group_desc structure
>> to avoid redundant struct params.
>>
> This fails to express why you're doing that, please see below.
>
>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
>> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> ---
>> drivers/pinctrl/qcom/Kconfig | 1 +
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 44 +++++++++++++++-----------------
>> 2 files changed, 22 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index ca6f68a..31c4aa6 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -351,6 +351,7 @@ config PINCTRL_LPASS_LPI
>> select PINMUX
>> select PINCONF
>> select GENERIC_PINCONF
>> + select GENERIC_PINCTRL_GROUPS
> This allow you to use struct group_desc, but what does that give you?
>
> I don't see a change where you're moving to use the common group_desc
> helpers that the framework supplies. Without that this just replace 3
> entries in struct lpi_pingroup with 4 entries in struct group_desc.
>
>
> Change looks good, iff it's followed by a transition to replace the
> driver's custom functions with pinctrl_generic_get_group_*().
>
> Regards,
> Bjorn
Okay. Will change and re send the patch set.
>
>> depends on GPIOLIB
>> help
>> This is the pinctrl, pinmux, pinconf and gpiolib driver for the
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> index 3c15f80..54750ba 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> @@ -51,11 +51,11 @@
>>
>> #define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
>> { \
>> - .name = "gpio" #id, \
>> - .pins = gpio##id##_pins, \
>> + .group.name = "gpio" #id, \
>> + .group.pins = gpio##id##_pins, \
>> .pin = id, \
>> .slew_offset = soff, \
>> - .npins = ARRAY_SIZE(gpio##id##_pins), \
>> + .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
>> .funcs = (int[]){ \
>> LPI_MUX_gpio, \
>> LPI_MUX_##f1, \
>> @@ -67,9 +67,7 @@
>> }
>>
>> struct lpi_pingroup {
>> - const char *name;
>> - const unsigned int *pins;
>> - unsigned int npins;
>> + struct group_desc group;
>> unsigned int pin;
>> /* Bit offset in slew register for SoundWire pins only */
>> int slew_offset;
>> @@ -150,20 +148,20 @@ enum sm8250_lpi_functions {
>> LPI_MUX__,
>> };
>>
>> -static const unsigned int gpio0_pins[] = { 0 };
>> -static const unsigned int gpio1_pins[] = { 1 };
>> -static const unsigned int gpio2_pins[] = { 2 };
>> -static const unsigned int gpio3_pins[] = { 3 };
>> -static const unsigned int gpio4_pins[] = { 4 };
>> -static const unsigned int gpio5_pins[] = { 5 };
>> -static const unsigned int gpio6_pins[] = { 6 };
>> -static const unsigned int gpio7_pins[] = { 7 };
>> -static const unsigned int gpio8_pins[] = { 8 };
>> -static const unsigned int gpio9_pins[] = { 9 };
>> -static const unsigned int gpio10_pins[] = { 10 };
>> -static const unsigned int gpio11_pins[] = { 11 };
>> -static const unsigned int gpio12_pins[] = { 12 };
>> -static const unsigned int gpio13_pins[] = { 13 };
>> +static int gpio0_pins[] = { 0 };
>> +static int gpio1_pins[] = { 1 };
>> +static int gpio2_pins[] = { 2 };
>> +static int gpio3_pins[] = { 3 };
>> +static int gpio4_pins[] = { 4 };
>> +static int gpio5_pins[] = { 5 };
>> +static int gpio6_pins[] = { 6 };
>> +static int gpio7_pins[] = { 7 };
>> +static int gpio8_pins[] = { 8 };
>> +static int gpio9_pins[] = { 9 };
>> +static int gpio10_pins[] = { 10 };
>> +static int gpio11_pins[] = { 11 };
>> +static int gpio12_pins[] = { 12 };
>> +static int gpio13_pins[] = { 13 };
>> static const char * const swr_tx_clk_groups[] = { "gpio0" };
>> static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
>> static const char * const swr_rx_clk_groups[] = { "gpio3" };
>> @@ -262,7 +260,7 @@ static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev,
>> {
>> struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
>>
>> - return pctrl->data->groups[group].name;
>> + return pctrl->data->groups[group].group.name;
>> }
>>
>> static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
>> @@ -272,8 +270,8 @@ static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
>> {
>> struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
>>
>> - *pins = pctrl->data->groups[group].pins;
>> - *num_pins = pctrl->data->groups[group].npins;
>> + *pins = pctrl->data->groups[group].group.pins;
>> + *num_pins = pctrl->data->groups[group].group.num_pins;
>>
>> return 0;
>> }
>> --
>> 2.7.4
>>
next prev parent reply other threads:[~2022-03-15 15:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-08 11:03 [PATCH v10 0/7] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
2022-03-08 11:03 ` [PATCH v10 1/7] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Srinivasa Rao Mandadapu
2022-03-08 11:03 ` [PATCH v10 2/7] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Srinivasa Rao Mandadapu
2022-03-08 11:03 ` [PATCH v10 3/7] pinctrl: qcom: Update macro name to LPI specific Srinivasa Rao Mandadapu
2022-03-08 17:46 ` Bjorn Andersson
2022-03-08 11:03 ` [PATCH v10 4/7] pinctrl: qcom: Update lpi pin group structure Srinivasa Rao Mandadapu
2022-03-08 17:55 ` Bjorn Andersson
2022-03-15 15:16 ` Srinivasa Rao Mandadapu [this message]
2022-03-08 11:03 ` [PATCH v10 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code Srinivasa Rao Mandadapu
2022-03-08 18:02 ` Bjorn Andersson
2022-03-15 15:18 ` Srinivasa Rao Mandadapu
2022-03-08 11:03 ` [PATCH v10 6/7] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu
2022-03-08 11:03 ` [PATCH v10 7/7] pinctrl: qcom: Update clock voting as optional Srinivasa Rao Mandadapu
2022-03-08 18:13 ` Bjorn Andersson
2022-03-15 15:33 ` Srinivasa Rao Mandadapu
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