From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7B6EC433FE for ; Wed, 25 May 2022 19:16:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344347AbiEYTQ1 (ORCPT ); Wed, 25 May 2022 15:16:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344770AbiEYTPR (ORCPT ); Wed, 25 May 2022 15:15:17 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9EEE4252A4 for ; Wed, 25 May 2022 12:14:24 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2FDE81424; Wed, 25 May 2022 12:14:24 -0700 (PDT) Received: from [10.57.81.38] (unknown [10.57.81.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6258A3F73D; Wed, 25 May 2022 12:14:23 -0700 (PDT) Message-ID: <35f95ba3-8a7b-7918-0f9d-e14274a5ffe9@arm.com> Date: Wed, 25 May 2022 20:14:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: Question about SPIs' interrupt trigger type restrictions Content-Language: en-GB To: richard clark , maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: From: Robin Murphy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022-05-25 11:01, richard clark wrote: > Hi Marc, > > For below code snippet about SPI interrupt trigger type: > > static int gic_set_type(struct irq_data *d, unsigned int type) > { > ... > /* SPIs have restrictions on the supported types */ > if ((range == SPI_RANGE || range == ESPI_RANGE) && > type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) > return -EINVAL; > ... > } > > We have a device at hand whose interrupt type is SPI, Falling edge > will trigger the interrupt. But the request_irq(50, handler, > IRQ_TYPE_EDGE_FALLING, ...) will return -EINVAL. > > The question is, why must the SPI interrupt use IRQ_TYPE_EDGE_RISING > instead of IRQ_TYPE_EDGE_FALLING? Because that's what the GIC architecture[1] says. From section 1.2.1 "Interrupt Types": "An interrupt that is edge-triggered has the following property: • It is asserted on detection of a rising edge of an interrupt signal and then, regardless of the state of the signal, remains asserted until the interrupt is acknowledged by software." External signals with the wrong polarity may need external logic to invert them (which might even be offered by the GIC implementation itself, e.g. [2]), but the programmer's model neither knows nor cares about such details, it only knows notions of "edge-triggered" and "level-sensitive", where from its point of view the asserted states are rising and high respectively. Robin. [1] https://developer.arm.com/documentation/ihi0069/latest [2] https://developer.arm.com/documentation/100336/0106/components-and-configuration/spi-collator/spi-collator-wires?lang=en