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X-CSE-ConnectionGUID: XWfS4veXTIKhHk6aicqvmg== X-CSE-MsgGUID: 3KROLYyRRqurZ6iPWnuAnQ== X-IronPort-AV: E=McAfee;i="6800,10657,11914"; a="101166040" X-IronPort-AV: E=Sophos;i="6.27,120,1787036400"; d="scan'208";a="101166040" Received: from fmviesa013.fm.intel.com ([10.60.135.153]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2026 23:43:27 -0700 X-CSE-ConnectionGUID: pY9orfd9R6qBMDUXknKN9g== X-CSE-MsgGUID: Chksm04BRyetykOJyAmKwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,120,1787036400"; d="scan'208";a="5179508" Received: from blu2-desk.sh.intel.com (HELO [10.239.156.26]) ([10.239.156.26]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2026 23:43:24 -0700 Message-ID: <360a128c-19b4-454e-b7a0-c96e3d47484f@linux.intel.com> Date: Thu, 24 Sep 2026 14:43:21 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] iommu/vt-d: Fix page table level calculation in compute_vasz_lg2_ss() To: Zhenzhong Duan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Cc: dwmw2@infradead.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, jgg@ziepe.ca, kevin.tian@intel.com, Joerg Roedel References: <20260825080002.117412-1-zhenzhong.duan@intel.com> Content-Language: en-US From: Baolu Lu In-Reply-To: <20260825080002.117412-1-zhenzhong.duan@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/25/26 16:00, Zhenzhong Duan wrote: > compute_vasz_lg2_ss() finds the optimal Second-Stage page table level by > intersecting the maximum guest address width (mgaw) with the hardware's > SAGAW capability register. > > The VT-d spec maps the SAGAW bit field positions as: > - Bit 1: 39-bit AGAW (3-level page table, top_level = 2) > - Bit 2: 48-bit AGAW (4-level page table, top_level = 3) > - Bit 3: 57-bit AGAW (5-level page table, top_level = 4) > > The fallback paths use bit shifts that are one position too large, > causing ffs() to select a deeper page table level than the mgaw window > requires: > > - mgaw > 39: "3 + ffs(sagaw >> 3)" evaluates to top_level = 4 (5-level) > instead of top_level = 3 (4-level) when hardware supports both > 48-bit (Bit 2) and 57-bit (Bit 3) AGAW. > - mgaw > 30: "2 + ffs(sagaw >> 2)" evaluates to top_level = 3 (4-level) > instead of top_level = 2 (3-level) when hardware supports both > 39-bit (Bit 1) and 48-bit (Bit 2) AGAW. > > In both cases the selected level is still one that the hardware advertises > in its SAGAW capability, so IOVA translation remains functionally correct. > However, an unnecessarily deep page table may be selected, adding an extra > level of page walk overhead and reducing TLB and cache efficiency without > providing any increase in addressable IOVA space beyond what the mgaw > window already caps. > > Fix by decreasing the shift offset by one in each fallback case, ensuring > ffs() targets the correct SAGAW bit position and selects the smallest > page table level that fully covers the mgaw range: > > - mgaw > 39: "2 + ffs(sagaw >> 2)" correctly yields top_level = 3 > - mgaw > 30: "1 + ffs(sagaw >> 1)" correctly yields top_level = 2 > > Fixes: d856f9d27885 ("iommupt/vtd: Allow VT-d to have a larger table top than the vasz requires") > Signed-off-by: Zhenzhong Duan > --- > drivers/iommu/intel/iommu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Queued for iommu/next. Thanks!