From: Neil Armstrong <neil.armstrong@linaro.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Andy Gross <agross@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, Abel Vesa <abel.vesa@linaro.org>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 2/3] arm64: dts: qcom: sm8550: add adsp, cdsp & mdss support nodes
Date: Thu, 17 Nov 2022 11:13:33 +0100 [thread overview]
Message-ID: <360dee55-8c40-2d65-ed4a-d14e66c92f9d@linaro.org> (raw)
In-Reply-To: <f4f53117-7f60-6f22-0e0f-bb4f8ee1ea9f@linaro.org>
On 16/11/2022 12:45, Konrad Dybcio wrote:
>
>
> On 16/11/2022 11:43, Neil Armstrong wrote:
>> This adds support for the aDSP, cDSP and MPSS Subsystems found in
>> the SM8550 SoC.
>>
>> The aDSP, cDSP and MPSS needs:
>> - smp2p support nodes to get event back from the subsystems
>> - remoteproc nodes with glink-edge subnodes providing all needed
>> resources to start and run the subsystems
>>
>> In addition, the MPSS Subsystem needs a rmtfs_mem dedicated
>> memory zone.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
> The title and commit message are misleading, you're either adding support or adding nodes. There is no such thing as "support nodes".
Yep you're right,
>
> The code looks good though, so with that fixed:
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Will fix for v2.
Thanks,
Neil
>
> Konrad
>
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 337 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 337 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index 9e00778bb600..cac3adc4504f 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -543,6 +543,15 @@ adspslpi_mem: adspslpi-region@9ea00000 {
>> /* Linux kernel image is loaded at 0xa8000000 */
>> + rmtfs_mem: rmtfs-region@d4a80000 {
>> + compatible = "qcom,rmtfs-mem";
>> + reg = <0x0 0xd4a80000 0x0 0x280000>;
>> + no-map;
>> +
>> + qcom,client-id = <1>;
>> + qcom,vmid = <15>;
>> + };
>> +
>> mpss_dsm_mem: mpss-dsm-region@d4d00000 {
>> compatible = "qcom,mpss-dsm-mem";
>> reg = <0x0 0xd4d00000 0x0 0x3300000>;
>> @@ -635,6 +644,89 @@ hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
>> };
>> };
>> + smp2p-adsp {
>> + compatible = "qcom,smp2p";
>> + qcom,smem = <443>, <429>;
>> + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
>> + IPCC_MPROC_SIGNAL_SMP2P
>> + IRQ_TYPE_EDGE_RISING>;
>> + mboxes = <&ipcc IPCC_CLIENT_LPASS
>> + IPCC_MPROC_SIGNAL_SMP2P>;
>> +
>> + qcom,local-pid = <0>;
>> + qcom,remote-pid = <2>;
>> +
>> + smp2p_adsp_out: master-kernel {
>> + qcom,entry-name = "master-kernel";
>> + #qcom,smem-state-cells = <1>;
>> + };
>> +
>> + smp2p_adsp_in: slave-kernel {
>> + qcom,entry-name = "slave-kernel";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>> + smp2p-cdsp {
>> + compatible = "qcom,smp2p";
>> + qcom,smem = <94>, <432>;
>> + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
>> + IPCC_MPROC_SIGNAL_SMP2P
>> + IRQ_TYPE_EDGE_RISING>;
>> + mboxes = <&ipcc IPCC_CLIENT_CDSP
>> + IPCC_MPROC_SIGNAL_SMP2P>;
>> +
>> + qcom,local-pid = <0>;
>> + qcom,remote-pid = <5>;
>> +
>> + smp2p_cdsp_out: master-kernel {
>> + qcom,entry-name = "master-kernel";
>> + #qcom,smem-state-cells = <1>;
>> + };
>> +
>> + smp2p_cdsp_in: slave-kernel {
>> + qcom,entry-name = "slave-kernel";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>> + smp2p-modem {
>> + compatible = "qcom,smp2p";
>> + qcom,smem = <435>, <428>;
>> + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
>> + IPCC_MPROC_SIGNAL_SMP2P
>> + IRQ_TYPE_EDGE_RISING>;
>> + mboxes = <&ipcc IPCC_CLIENT_MPSS
>> + IPCC_MPROC_SIGNAL_SMP2P>;
>> +
>> + qcom,local-pid = <0>;
>> + qcom,remote-pid = <1>;
>> +
>> + smp2p_modem_out: master-kernel {
>> + qcom,entry-name = "master-kernel";
>> + #qcom,smem-state-cells = <1>;
>> + };
>> +
>> + smp2p_modem_in: slave-kernel {
>> + qcom,entry-name = "slave-kernel";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + ipa_smp2p_out: ipa-ap-to-modem {
>> + qcom,entry-name = "ipa";
>> + #qcom,smem-state-cells = <1>;
>> + };
>> +
>> + ipa_smp2p_in: ipa-modem-to-ap {
>> + qcom,entry-name = "ipa";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>> soc: soc@0 {
>> #address-cells = <2>;
>> #size-cells = <2>;
>> @@ -1388,6 +1480,48 @@ tcsr: clock-controller@1fc0000 {
>> #reset-cells = <1>;
>> };
>> + remoteproc_mpss: remoteproc@4080000 {
>> + compatible = "qcom,sm8550-mpss-pas";
>> + reg = <0x0 0x04080000 0x0 0x4040>;
>> +
>> + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "wdog", "fatal", "ready", "handover",
>> + "stop-ack", "shutdown-ack";
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "xo";
>> +
>> + power-domains = <&rpmhpd SM8550_CX>,
>> + <&rpmhpd SM8550_MSS>;
>> + power-domain-names = "cx", "mss";
>> +
>> + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
>> +
>> + memory-region = <&mpss_mem &q6_mpss_dtb_mem>;
>> +
>> + qcom,qmp = <&aoss_qmp>;
>> +
>> + qcom,smem-states = <&smp2p_modem_out 0>;
>> + qcom,smem-state-names = "stop";
>> +
>> + status = "disabled";
>> +
>> + glink-edge {
>> + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
>> + IPCC_MPROC_SIGNAL_GLINK_QMP
>> + IRQ_TYPE_EDGE_RISING>;
>> + mboxes = <&ipcc IPCC_CLIENT_MPSS
>> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> + label = "mpss";
>> + qcom,remote-pid = <1>;
>> + };
>> + };
>> +
>> lpass_lpiaon_noc: interconnect@7400000 {
>> compatible = "qcom,sm8550-lpass-lpiaon-noc";
>> reg = <0x0 0x07400000 0x0 0x19080>;
>> @@ -2865,12 +2999,215 @@ system-cache-controller@25000000 {
>> interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
>> };
>> + remoteproc_adsp: remoteproc@30000000 {
>> + compatible = "qcom,sm8550-adsp-pas";
>> + reg = <0x0 0x30000000 0x0 0x100>;
>> +
>> + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "wdog", "fatal", "ready",
>> + "handover", "stop-ack";
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "xo";
>> +
>> + power-domains = <&rpmhpd SM8550_LCX>,
>> + <&rpmhpd SM8550_LMX>;
>> + power-domain-names = "lcx", "lmx";
>> +
>> + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
>> +
>> + memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>;
>> +
>> + qcom,qmp = <&aoss_qmp>;
>> +
>> + qcom,smem-states = <&smp2p_adsp_out 0>;
>> + qcom,smem-state-names = "stop";
>> +
>> + status = "disabled";
>> +
>> + remoteproc_adsp_glink: glink-edge {
>> + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
>> + IPCC_MPROC_SIGNAL_GLINK_QMP
>> + IRQ_TYPE_EDGE_RISING>;
>> + mboxes = <&ipcc IPCC_CLIENT_LPASS
>> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +
>> + label = "lpass";
>> + qcom,remote-pid = <2>;
>> +
>> + fastrpc {
>> + compatible = "qcom,fastrpc";
>> + qcom,glink-channels = "fastrpcglink-apps-dsp";
>> + label = "adsp";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + compute-cb@3 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <3>;
>> + iommus = <&apps_smmu 0x1003 0x80>,
>> + <&apps_smmu 0x1063 0x0>;
>> + };
>> +
>> + compute-cb@4 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <4>;
>> + iommus = <&apps_smmu 0x1004 0x80>,
>> + <&apps_smmu 0x1064 0x0>;
>> + };
>> +
>> + compute-cb@5 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <5>;
>> + iommus = <&apps_smmu 0x1005 0x80>,
>> + <&apps_smmu 0x1065 0x0>;
>> + };
>> +
>> + compute-cb@6 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <6>;
>> + iommus = <&apps_smmu 0x1006 0x80>,
>> + <&apps_smmu 0x1066 0x0>;
>> + };
>> +
>> + compute-cb@7 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <7>;
>> + iommus = <&apps_smmu 0x1007 0x80>,
>> + <&apps_smmu 0x1067 0x0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> nsp_noc: interconnect@320c0000 {
>> compatible = "qcom,sm8550-nsp-noc";
>> reg = <0x0 0x320C0000 0x0 0xE080>;
>> #interconnect-cells = <2>;
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> };
>> +
>> + remoteproc_cdsp: remoteproc@32300000 {
>> + compatible = "qcom,sm8550-cdsp-pas";
>> + reg = <0x0 0x32300000 0x0 0x1400000>;
>> +
>> + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "wdog", "fatal", "ready",
>> + "handover", "stop-ack";
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "xo";
>> +
>> + power-domains = <&rpmhpd SM8550_CX>,
>> + <&rpmhpd SM8550_MXC>,
>> + <&rpmhpd SM8550_NSP>;
>> + power-domain-names = "cx", "mxc", "nsp";
>> +
>> + interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
>> +
>> + memory-region = <&cdsp_mem &q6_cdsp_dtb_mem>;
>> +
>> + qcom,qmp = <&aoss_qmp>;
>> +
>> + qcom,smem-states = <&smp2p_cdsp_out 0>;
>> + qcom,smem-state-names = "stop";
>> +
>> + status = "disabled";
>> +
>> + glink-edge {
>> + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
>> + IPCC_MPROC_SIGNAL_GLINK_QMP
>> + IRQ_TYPE_EDGE_RISING>;
>> + mboxes = <&ipcc IPCC_CLIENT_CDSP
>> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +
>> + label = "cdsp";
>> + qcom,remote-pid = <5>;
>> +
>> + fastrpc {
>> + compatible = "qcom,fastrpc";
>> + qcom,glink-channels = "fastrpcglink-apps-dsp";
>> + label = "cdsp";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> +
>> + compute-cb@1 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <1>;
>> + iommus = <&apps_smmu 0x1961 0x0>,
>> + <&apps_smmu 0x0c01 0x20>,
>> + <&apps_smmu 0x19c1 0x10>;
>> + };
>> +
>> + compute-cb@2 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <2>;
>> + iommus = <&apps_smmu 0x1962 0x0>,
>> + <&apps_smmu 0x0c02 0x20>,
>> + <&apps_smmu 0x19c2 0x10>;
>> + };
>> +
>> + compute-cb@3 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <3>;
>> + iommus = <&apps_smmu 0x1963 0x0>,
>> + <&apps_smmu 0x0c03 0x20>,
>> + <&apps_smmu 0x19c3 0x10>;
>> + };
>> +
>> + compute-cb@4 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <4>;
>> + iommus = <&apps_smmu 0x1964 0x0>,
>> + <&apps_smmu 0x0c04 0x20>,
>> + <&apps_smmu 0x19c4 0x10>;
>> + };
>> +
>> + compute-cb@5 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <5>;
>> + iommus = <&apps_smmu 0x1965 0x0>,
>> + <&apps_smmu 0x0c05 0x20>,
>> + <&apps_smmu 0x19c5 0x10>;
>> + };
>> +
>> + compute-cb@6 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <6>;
>> + iommus = <&apps_smmu 0x1966 0x0>,
>> + <&apps_smmu 0x0c06 0x20>,
>> + <&apps_smmu 0x19c6 0x10>;
>> + };
>> +
>> + compute-cb@7 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <7>;
>> + iommus = <&apps_smmu 0x1967 0x0>,
>> + <&apps_smmu 0x0c07 0x20>,
>> + <&apps_smmu 0x19c7 0x10>;
>> + };
>> +
>> + compute-cb@8 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <8>;
>> + iommus = <&apps_smmu 0x1968 0x0>,
>> + <&apps_smmu 0x0c08 0x20>,
>> + <&apps_smmu 0x19c8 0x10>;
>> + };
>> +
>> + /* note: secure cb9 in downstream */
>> + };
>> + };
>> + };
>> };
>> thermal-zones {
>>
next prev parent reply other threads:[~2022-11-17 10:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-16 10:43 [PATCH 0/3] arm64: dts: qcom: Add ADSP, CDSP & MDSS support to SM8550 and MTP board Neil Armstrong
2022-11-16 10:43 ` [PATCH 1/3] arm64: dts: qcom: sm8550: Add interconnect path to SCM node Neil Armstrong
2022-11-16 11:46 ` Konrad Dybcio
2022-11-16 10:43 ` [PATCH 2/3] arm64: dts: qcom: sm8550: add adsp, cdsp & mdss support nodes Neil Armstrong
2022-11-16 11:45 ` Konrad Dybcio
2022-11-17 10:13 ` Neil Armstrong [this message]
2022-11-16 10:43 ` [PATCH 3/3] arm64: dts: qcom: sm8550-mtp: enable adsp, cdsp & mdss Neil Armstrong
2022-11-16 11:46 ` Konrad Dybcio
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=360dee55-8c40-2d65-ed4a-d14e66c92f9d@linaro.org \
--to=neil.armstrong@linaro.org \
--cc=abel.vesa@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®