From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Rob Herring <robh@kernel.org>,
Mao Jinlong <jinlong.mao@oss.qualcomm.com>,
Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Subject: Re: [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes
Date: Tue, 6 Jan 2026 09:29:50 +0800 [thread overview]
Message-ID: <3618ea01-1fc4-4fc8-a0d7-23336c633435@oss.qualcomm.com> (raw)
In-Reply-To: <20251103-enable-ctcu-for-monaco-v4-2-92ff83201584@oss.qualcomm.com>
On 11/3/2025 3:06 PM, Jie Gan wrote:
> Add CTCU and ETR nodes in DT to enable expected functionalities.
>
Gentle ping, this patch should go through QCOM tree.
> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/monaco.dtsi | 153 +++++++++++++++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 816fa2af8a9a..1966dfad2dcc 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2483,6 +2483,35 @@ lpass_ag_noc: interconnect@3c40000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ctcu@4001000 {
> + compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
> + reg = <0x0 0x04001000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + ctcu_in0: endpoint {
> + remote-endpoint = <&etr0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + ctcu_in1: endpoint {
> + remote-endpoint = <&etr1_out>;
> + };
> + };
> + };
> + };
> +
> stm@4002000 {
> compatible = "arm,coresight-stm", "arm,primecell";
> reg = <0x0 0x04002000 0x0 0x1000>,
> @@ -2677,6 +2706,122 @@ qdss_funnel_out: endpoint {
> };
> };
>
> + replicator@4046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x04046000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + qdss_rep_in: endpoint {
> + remote-endpoint = <&swao_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + qdss_rep_out0: endpoint {
> + remote-endpoint = <&etr_rep_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@4048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x04048000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04c0 0x00>;
> +
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr0_in: endpoint {
> + remote-endpoint = <&etr_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr0_out: endpoint {
> + remote-endpoint = <&ctcu_in0>;
> + };
> + };
> + };
> + };
> +
> + replicator@404e000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x0404e000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + etr_rep_in: endpoint {
> + remote-endpoint = <&qdss_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + etr_rep_out0: endpoint {
> + remote-endpoint = <&etr0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + etr_rep_out1: endpoint {
> + remote-endpoint = <&etr1_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@404f000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x0404f000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04a0 0x40>;
> +
> + arm,scatter-gather;
> + arm,buffer-size = <0x400000>;
> +
> + in-ports {
> + port {
> + etr1_in: endpoint {
> + remote-endpoint = <&etr_rep_out1>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr1_out: endpoint {
> + remote-endpoint = <&ctcu_in1>;
> + };
> + };
> + };
> + };
> +
> tpdm@4841000 {
> compatible = "qcom,coresight-tpdm", "arm,primecell";
> reg = <0x0 0x04841000 0x0 0x1000>;
> @@ -3106,6 +3251,14 @@ out-ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + port@0 {
> + reg = <0>;
> +
> + swao_rep_out0: endpoint {
> + remote-endpoint = <&qdss_rep_in>;
> + };
> + };
> +
> port@1 {
> reg = <1>;
>
>
next prev parent reply other threads:[~2026-01-06 1:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 7:06 [PATCH v4 0/2] Enable CTCU device for QCS8300 Jie Gan
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
2025-11-10 1:29 ` Jie Gan
2025-11-21 8:26 ` Jie Gan
2025-12-19 9:08 ` Jie Gan
2025-12-19 12:11 ` Suzuki K Poulose
2025-12-19 12:27 ` Konrad Dybcio
2025-11-03 7:06 ` [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Jie Gan
2025-12-22 3:06 ` Jie Gan
2026-01-06 1:29 ` Jie Gan [this message]
2026-01-09 11:02 ` Jie Gan
2025-12-19 14:01 ` (subset) [PATCH v4 0/2] Enable CTCU device for QCS8300 Suzuki K Poulose
2026-01-10 19:11 ` Bjorn Andersson
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