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Mon, 02 Nov 2026 07:08:38 -0800 (PST) Received: from [192.168.226.93] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b52f3c2934sm444634a12.33.2026.11.02.07.08.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Nov 2026 07:08:37 -0800 (PST) Message-ID: <362884cb-71c1-4d12-b315-9923118c8564@oss.qualcomm.com> Date: Mon, 2 Nov 2026 16:08:33 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/12] dt-bindings: clock: qcom: Add bindings for PDM GP_MN clock divider To: Taniya Das , Krzysztof Kozlowski Cc: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Linus Walleij , Richard Cochran , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org References: <20261026-b4-pdm_clk_gp_mnd_v2-v2-0-ff8e4bc8d567@oss.qualcomm.com> <20261026-b4-pdm_clk_gp_mnd_v2-v2-1-ff8e4bc8d567@oss.qualcomm.com> <20261027-inescapable-rough-viper-6cd56d@quoll> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAyMDA2MCBTYWx0ZWRfX2QsUQLQn8jcM fgMqwI+40y3k7KU9l9uGt5o1VobzVlx+sKU6hjdDmjRKvK+trWqxuOb8c80FLq+uu0DTl6aTIkw A2iRXsq3SOD0yup3UoEvJfomnzuaPRXILwRBQRSlHBfCUoynASeYXl2CfUqbSXe1HN3OKHlhSCN ZW3OHEvfNM0GN088XVGVQBPftA2YDEMDd23+8pghVSCnBnEPaAx5LjzZG2ImHCiUqh2gkFuaE6y w9W7yCC/q3BGYrazcWI4+ownIAZpQBks9/66ykkvYIZsQd48gM7BhtMByHJULRFakaxugoQXOPR TArWPGLcwXeF+68FrEb91bKicDA67ICoYDMXts9vySi8lmZ1aPlbuswLC1pVMeJA4uS92hEe8mj wOlCYPlroOaj+NJGdhezLFQtPrjIWbrcTqpGrIGQnbbCVPHJZgx/eRDSqT/auKZB1R4wmVHKFod xCsIyySJNn414vY1lxQ== X-Proofpoint-GUID: I2wVARkOuo9wVvoywjJ5dASSwg6oMPn4 X-Authority-Analysis: v=2.4 cv=FZmiV5+6 c=1 sm=1 tr=0 ts=6ae8a777 cx=c_pps a=wuOIiItHwq1biOnFUQQHKA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=fjKjonZ3CYBpfGIA-1YA:9 a=QEXdDO2ut3YA:10 a=XD7yVLdPMpWraOa8Un9W:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAyMDA2MCBTYWx0ZWRfXw9KLaJbw5Scq D8V1fS9T1V99q5nZWxOMHDQWdgukdklHLQgvhn/0ESxFfOoByKofptpf3Vb8zCdh7V4tIs5bCh9 co65yD3xOe/UwtQoVydX7ZT4ANd14gM= X-Proofpoint-ORIG-GUID: I2wVARkOuo9wVvoywjJ5dASSwg6oMPn4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-02_04,2026-11-02_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611020060 On 10/29/26 11:57 AM, Taniya Das wrote: > > > On 10/28/2026 12:17 AM, Krzysztof Kozlowski wrote: >> On Mon, Oct 26, 2026 at 04:59:27PM +0530, Taniya Das wrote: >>> Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN >>> clock divider. The hardware generates a fractional output frequency >>> from a fixed input clock (typically TCXO4) using the relation >>> Fout = Fin * (M / N), with duty cycle controlled by a separate D >>> register. The clock output is routed over a gpio controlled pin. >>> >>> Signed-off-by: Taniya Das >>> --- [...] >>> + assigned-clocks: >>> + maxItems: 1 >>> + description: Parent clock phandle used to set the input frequency. >>> + >>> + assigned-clock-rates: >>> + maxItems: 1 >>> + description: | >>> + Rate for the parent clock in Hz. >>> + Supported rates: 19200000, 9600000, 6400000, 4800000. >> >> Neither assigned-clocks nor assigned-clock-rates should be needed. >> Parent clock is outside of scope of this binding. >> > > Sure I will remove, but the parent clock input is a requirement of the > Hardware and the output of this module entirely depends on the above > ranges of frequencies mentioned and that is the reason to keep the rates > specifically. I will capture it in the description and hope that should > be fine. So this is essentially xo, xo/2, xo/3, xo/4. The gcc_pdm_xo4_div_clk_src you added is defined as a 4-wide divider - do we need to limit that divider's range, or would div=0b1111=xo/15 also work? Konrad