From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E97D7C433E1 for ; Thu, 9 Jul 2020 09:14:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D43C2206C3 for ; Thu, 9 Jul 2020 09:14:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726285AbgGIJOo (ORCPT ); Thu, 9 Jul 2020 05:14:44 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7827 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726122AbgGIJOn (ORCPT ); Thu, 9 Jul 2020 05:14:43 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 19FFA74278D008C4810B; Thu, 9 Jul 2020 17:14:40 +0800 (CST) Received: from [127.0.0.1] (10.174.186.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 9 Jul 2020 17:14:29 +0800 Subject: Re: [PATCH v1 2/2] arm64: tlb: Use the TLBI RANGE feature in arm64 To: , , , , , , CC: , , , , , , , , References: <20200709091054.1698-1-yezhenyu2@huawei.com> <20200709091054.1698-3-yezhenyu2@huawei.com> From: Zhenyu Ye Message-ID: <362990d2-3948-9820-e2d9-aa1ff1c8b068@huawei.com> Date: Thu, 9 Jul 2020 17:14:28 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20200709091054.1698-3-yezhenyu2@huawei.com> Content-Type: text/plain; charset="gbk" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.186.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020/7/9 17:10, Zhenyu Ye wrote: > + /* > + * When cpu does not support TLBI RANGE feature, we flush the tlb > + * entries one by one at the granularity of 'stride'. > + * When cpu supports the TLBI RANGE feature, then: > + * 1. If pages is odd, flush the first page through non-RANGE > + * instruction; > + * 2. For remaining pages: The minimum range granularity is decided > + * by 'scale', so we can not flush all pages by one instruction > + * in some cases. > + * > + * For example, when the pages = 0xe81a, let's start 'scale' from > + * maximum, and find right 'num' for each 'scale': > + * > + * When scale = 3, we can flush no pages because the minumum > + * range is 2^(5*3 + 1) = 0x10000. > + * When scale = 2, the minimum range is 2^(5*2 + 1) = 0x800, we can > + * flush 0xe800 pages this time, the num = 0xe800/0x800 - 1 = 0x1c. > + * Remain pages is 0x1a; > + * When scale = 1, the minimum range is 2^(5*1 + 1) = 0x40, no page > + * can be flushed. > + * When scale = 0, we flush the remaining 0x1a pages, the num = > + * 0x1a/0x2 - 1 = 0xd. > + * > + * However, in most scenarios, the pages = 1 when flush_tlb_range() is > + * called. Start from scale = 3 or other proper value (such as scale = > + * ilog2(pages)), will incur extra overhead. > + * So increase 'scale' from 0 to maximum, the flush order is exactly > + * opposite to the example. > + */ The comments may be too long, probably should be moved to commit messages. Thanks, Zhenyu