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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e5d4b0sm10933059f8f.89.2025.04.28.05.26.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Apr 2025 05:26:17 -0700 (PDT) Message-ID: <364500a3-3343-42c2-a0cb-05a1bf39936c@linaro.org> Date: Mon, 28 Apr 2025 13:26:16 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: media: qcom,x1e80100-camss: Fixup csiphy supply names To: Krzysztof Kozlowski Cc: Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , dmitry.baryshkov@oss.qualcomm.com, loic.poulain@oss.qualcomm.com, vladimir.zapolskiy@linaro.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250426-b4-media-committers-25-04-25-camss-supplies-v3-0-19e5e72ffc3e@linaro.org> <20250426-b4-media-committers-25-04-25-camss-supplies-v3-1-19e5e72ffc3e@linaro.org> <20250428-lovely-flawless-grasshopper-bacbfa@kuoka> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20250428-lovely-flawless-grasshopper-bacbfa@kuoka> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 28/04/2025 08:14, Krzysztof Kozlowski wrote: > Block has VDD_A_CSI_0_1_1P2 input, not separate one for CSI0 and CS1. > I don't get what is the benefit of this and commit msg does not help me > to understand such choice. > > On IRC I clarified you could have less supplies in the binding than > number of actual pins, to make things simpler and more consistent, but > you did here reverse: more supplies which do not exist. So the idea here is to make a consistent - csiphy#-voltage-XpY Which means that each PHY will have voltage rail names like vdd-csiphy0-0p8 vdd-csiphy0-1p2 vdd-csiphy0-1p8 Irrespective of the SoC pin name. The motivation for that is to have the names be consistent across SoCs which is I believe what we have discussed should be the case. That means that each phy will have its own named set of voltage rails, consistently named across SoCs even if the pin-name is shared by the PHYs on the SoC pinout. Is that not the namespace consistency you've been looking for ? --- bod