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([2a05:6e02:1041:c10:2a30:223c:d73b:565a]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-45b940bbc0dsm89079915e9.2.2025.09.03.07.53.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Sep 2025 07:53:57 -0700 (PDT) Message-ID: <3659b492-c135-4fe1-9ffe-70877e4da0f5@linaro.org> Date: Wed, 3 Sep 2025 16:53:56 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms To: =?UTF-8?Q?Nuno_S=C3=A1?= , jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org Cc: linux-iio@vger.kernel.org, s32@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com References: <20250903102756.1748596-1-daniel.lezcano@linaro.org> <20250903102756.1748596-3-daniel.lezcano@linaro.org> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Nuno, On 03/09/2025 13:20, Nuno Sá wrote: > On Wed, 2025-09-03 at 12:27 +0200, Daniel Lezcano wrote: >> From: Stefan-Gabriel Mirea >> >> The NXP S32G2 and S32G3 platforms integrate a successive approximation >> register (SAR) ADC. Two instances are available, each providing 8 >> multiplexed input channels with 12-bit resolution. The conversion rate >> is up to 1 Msps depending on the configuration and sampling window. >> >> The SAR ADC supports raw, buffer, and trigger modes. It can operate >> in both single-shot and continuous conversion modes, with optional >> hardware triggering through the cross-trigger unit (CTU) or external >> events. An internal prescaler allows adjusting the sampling clock, >> while per-channel programmable sampling times provide fine-grained >> trade-offs between accuracy and latency. Automatic calibration is >> performed at probe time to minimize offset and gain errors. >> >> The driver is derived from the BSP implementation and has been partly >> rewritten to comply with upstream requirements. For this reason, all >> contributors are listed as co-developers, while the author refers to >> the initial BSP driver file creator. >> >> All modes have been validated on the S32G274-RDB2 platform using an >> externally generated square wave captured by the ADC. Tests covered >> buffered streaming via IIO, trigger synchronization, and accuracy >> verification against a precision laboratory signal source. >> >> Co-developed-by: Alexandru-Catalin Ionita >> Signed-off-by: Alexandru-Catalin Ionita >> Co-developed-by: Ciprian Costea >> Signed-off-by: Ciprian Costea >> Co-developed-by: Radu Pirea (NXP OSS) >> Signed-off-by: Radu Pirea (NXP OSS) >> Signed-off-by: Stefan-Gabriel Mirea >> Co-developed-by: Daniel Lezcano >> Signed-off-by: Daniel Lezcano >> --- > > Hi David, s/David/Daniel/ :) > Just some minor review for now... Whow, thanks for fast review ! [ ... ] >> +static int nxp_sar_adc_dma_probe(struct device *dev, struct nxp_sar_adc >> *info) >> +{ >> + struct device *dev_dma; >> + int ret; >> + u8 *rx_buf; >> + >> + info->dma_chan = devm_dma_request_chan(dev, "rx"); >> + if (IS_ERR(info->dma_chan)) >> + return PTR_ERR(info->dma_chan); >> + >> + dev_dma = info->dma_chan->device->dev; >> + rx_buf = dma_alloc_coherent(dev_dma, NXP_SAR_ADC_DMA_BUFF_SZ, >> +     &info->rx_dma_buf, GFP_KERNEL); >> + if (!rx_buf) >> + return -ENOMEM; >> + > > The above needs some discussion at the very least. Have you considered the IIO > DMA buffer interface? It should be extendable to accommodate any particularity > of your usecase (or we should at least discuss it). > > With it, you also gain a userspace interface where you can actually share DMA > buffers in a zero copy fashion. You can also share these buffers with USB > gadgets. For instance, with libiio, you would be able to fetch samples from your > host machine (through USB) in a very fast way (zero copy between IIO and USB). > > Setting up DMA to then "having" to push it to a SW buffer and needing a syscall > to retrieve the data seems counter-productive. I'm not very used to dma. If there is a better implementation to put in place I'll be glad to take any suggestion to understand the approach. Is there any driver using the IIO DMA buffer interface I can refer to ? [ ... ] -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog