From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754927AbdESN3S (ORCPT ); Fri, 19 May 2017 09:29:18 -0400 Received: from foss.arm.com ([217.140.101.70]:43930 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750764AbdESN3R (ORCPT ); Fri, 19 May 2017 09:29:17 -0400 Subject: Re: [PATCH] coresight: tmc: Configure DMA mask appropriately To: Robin Murphy , mathieu.poirier@linaro.org References: Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org From: Suzuki K Poulose Message-ID: <3659c485-88ca-4fa9-ce7b-dfb77d8a050a@arm.com> Date: Fri, 19 May 2017 14:29:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/05/17 16:14, Robin Murphy wrote: > Before making any DMA API calls, the ETR driver should really be setting > its masks to ensure that DMA is possible. Especially since it can > address more than the 32-bit default mask set by the AMBA bus code. > > Signed-off-by: Robin Murphy > --- > drivers/hwtracing/coresight/coresight-tmc.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c > index d8517d2a968c..864488793f09 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.c > +++ b/drivers/hwtracing/coresight/coresight-tmc.c > @@ -362,6 +362,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > desc.type = CORESIGHT_DEV_TYPE_SINK; > desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; > desc.ops = &tmc_etr_cs_ops; > + /* > + * ETR configuration uses a 40-bit AXI master in place of > + * the embedded SRAM of ETB/ETF. > + */ > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); > + if (ret) > + goto out; > } else { > desc.type = CORESIGHT_DEV_TYPE_LINKSINK; > desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; > Tested this patch on Juno, with the SMMU enabled for the etr. I was able to allocate 32M using (the CMA was only 16M). FWIW : Tested-by: Suzuki K Poulose