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Mon, 16 Dec 2024 06:46:40 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BG6keZu011347 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 16 Dec 2024 06:46:40 GMT Received: from [10.239.132.205] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 15 Dec 2024 22:46:33 -0800 Message-ID: <365c24e5-5482-4ee8-9dfb-36af96454d2d@quicinc.com> Date: Mon, 16 Dec 2024 14:46:31 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300 To: Dmitry Baryshkov CC: Bjorn Andersson , Linus Walleij , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Jingyi Wang" , Konrad Dybcio , , , , , , Krzysztof Kozlowski References: <20241212-correct_gpio_ranges-v1-0-c5f20d61882f@quicinc.com> From: Lijuan Gao In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ANd-U4zH-U6IysopODhS89HLFQ3969Yd X-Proofpoint-ORIG-GUID: ANd-U4zH-U6IysopODhS89HLFQ3969Yd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxscore=0 adultscore=0 clxscore=1011 bulkscore=0 mlxlogscore=814 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412160054 在 12/12/2024 5:34 PM, Dmitry Baryshkov 写道: > On Thu, Dec 12, 2024 at 05:23:59PM +0800, Lijuan Gao wrote: >> The UFS_RESET pin is expected to be wired to the reset pin of the >> primary UFS memory, it's a general purpose output pin. Reorder it and >> expose it as a gpio, so that the UFS driver can toggle it. > > I don't see pins being reordered. Please correct your commit messages. > Understood, I will update the commit message in next patch, thanks! >> >> The QCS615 TLMM pin controller has GPIOs 0-122, so correct the >> gpio-rangs to 124. >> >> The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the >> gpio-rangs to 134. >> >> Signed-off-by: Lijuan Gao >> --- >> Lijuan Gao (6): >> dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615 >> dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300 >> pinctrl: qcom: correct the number of ngpios for QCS615 >> pinctrl: qcom: correct the number of ngpios for QCS8300 >> arm64: dts: qcom: correct gpio-ranges for QCS615 >> arm64: dts: qcom: correct gpio-ranges for QCS8300 >> >> Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +- >> Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +- >> drivers/pinctrl/qcom/pinctrl-qcs615.c | 2 +- >> drivers/pinctrl/qcom/pinctrl-qcs8300.c | 2 +- >> 6 files changed, 6 insertions(+), 6 deletions(-) >> --- >> base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07 >> change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7 >> >> Best regards, >> -- >> Lijuan Gao >> > -- Thx and BRs Lijuan Gao