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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbef86df9sm114178366b.10.2026.01.28.02.46.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Jan 2026 02:46:38 -0800 (PST) Message-ID: <366fe074-3355-4c9b-b60f-4f7de0ba6a0f@oss.qualcomm.com> Date: Wed, 28 Jan 2026 11:46:36 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties To: Neil Armstrong , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260128-topic-sm8650-upstream-cpu-props-v1-0-9fbb5efe7f07@linaro.org> <20260128-topic-sm8650-upstream-cpu-props-v1-2-9fbb5efe7f07@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260128-topic-sm8650-upstream-cpu-props-v1-2-9fbb5efe7f07@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=YNWSCBGx c=1 sm=1 tr=0 ts=6979e910 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=eHTvguOgXxrd6O_h2noA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: i-vskI8CFSz14SbwEumrv6Utq8s2WeeH X-Proofpoint-GUID: i-vskI8CFSz14SbwEumrv6Utq8s2WeeH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI4MDA4NyBTYWx0ZWRfX661YkFvKVUXY kIeQnGUR4hn+CQR1aT91CitZsnh97q3+VJJGFLWtjEmch3xPOJVpq5q5GxwdVJAnFshVi0joiK6 udpCCgr8yBu66vsgvdEGj5tSdgIEy95Sgs8P3n+mCBLeHKEoVqcVehwOjafqvmIjB3vgiGkv7ic N0ISCMgIiN5IzD1pOwnFqO+BLVaZVGQlUJQTTi1ng41cIlq3gjKuPValnAsBsswu0kaBMu1//Qv ZHefN0c9MEjM8u9HspFAvcLCzUD9VsYNApdE+W7wfAiP9uoLJeLtG9eKyDI/HfKLFDVbsYjUhp0 l4RAVPvO8qrsAj2nh6M/+x3dZb/JCiTITPsi8oRvomIrl883uu/ceIu5Q1epKVSWt72A9cjZjWJ DFdRQ8rzFaWn0xazStfM5/rEpOgVqWrj0IBu5pjUxtLZzZaUxGkYBLiak9BqPT3mor/J6Bc3gJI uzGRGbweI/D+SUIYhJw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_02,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601280087 On 1/28/26 11:33 AM, Neil Armstrong wrote: > Add the L1 cache size and its line size (cache-size and > cache-line-size) with the corresponding L1-I cache and L1-D cache. > > L1 cache is unified, but clidr_el1 register (get_cache_type) tells that > L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and > d-cache-line-size and cache-line-size of L3 cache is specified. > > All cache line sizes were confirmed by checking ccsidr_el1. > > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 56 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 8671c25dd68f..f8563ec79dc6 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -75,6 +75,11 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a520"; > reg = <0 0>; > > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + > clocks = <&cpufreq_hw 0>; > > power-domains = <&cpu_pd0>; > @@ -103,11 +108,15 @@ l2_0: l2-cache { > cache-level = <2>; > cache-unified; > next-level-cache = <&l3_0>; > + cache-size = <262144>; This should be 512 kiB, shared for c0/1, according to a block diagram Everything else lgtm, although I can't find a source for the cache*line* sizes Konrad