From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753034AbcGLA5n (ORCPT ); Mon, 11 Jul 2016 20:57:43 -0400 Received: from mga11.intel.com ([192.55.52.93]:61300 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751698AbcGLA5l convert rfc822-to-8bit (ORCPT ); Mon, 11 Jul 2016 20:57:41 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,348,1464678000"; d="scan'208";a="137542417" From: "Chen, Yu C" To: "Pan, Jacob jun" , Ingo Molnar CC: "'Len Brown'" , Jacob Pan , "H. Peter Anvin" , Peter Zijlstra , "x86@kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: Hi, Ingo, would you please help drop the TSC MSR calibration patch Thread-Topic: Hi, Ingo, would you please help drop the TSC MSR calibration patch Thread-Index: AQHR24pJ32w7o8pQOU+UwPcKCV3SbaATGFUAgAAeCICAALFrUA== Date: Tue, 12 Jul 2016 00:57:38 +0000 Message-ID: <36DF59CE26D8EE47B0655C516E9CE64028780331@shsmsx102.ccr.corp.intel.com> References: <36DF59CE26D8EE47B0655C516E9CE6402878009C@shsmsx102.ccr.corp.intel.com> <20160711083540.02f86b3f@icelake> <20160711193103.GA27007@gmail.com> <20160711141833.352e16e3@icelake> In-Reply-To: <20160711141833.352e16e3@icelake> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTJiY2JkNTEtZThiNy00NGMzLThkODMtYjlkZDk0YTk0YjI1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Im5OcWVObmFEcDBIekhcLzFFTWJVbkQ5N1VqSFRKY1wvT1ZiYVFwNm9MMXpOND0ifQ== x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, > -----Original Message----- > From: Pan, Jacob jun > Sent: Tuesday, July 12, 2016 5:19 AM > To: Ingo Molnar > Cc: Chen, Yu C; 'Len Brown'; Jacob Pan; H. Peter Anvin; Peter Zijlstra; > x86@kernel.org; linux-kernel@vger.kernel.org; Pan, Jacob jun > Subject: Re: Hi, Ingo, would you please help drop the TSC MSR calibration patch > > On Mon, 11 Jul 2016 21:31:04 +0200 > Ingo Molnar wrote: > > > > > * Jacob Pan wrote: > > > > > On Mon, 11 Jul 2016 07:59:19 -0700 > > > "Chen, Yu C" wrote: > > > > > > > Currently it is in your x86/timer tree: > > > > > > > > commit fc273eeef314cdaf0ac992b400d126f8184a4d1c > > > > Author: Len Brown > > > > Date: Fri Jun 17 01:22:49 2016 -0400 > > > > > > > > x86/tsc_msr: Extend to include Intel Core Architecture > > > > > > > > > > > > Previously we found this patch might decrease the performance on > > > > one of our servers, due to the small gap between using old PIT > > > > calibration and new MSR calibration method, so we currently would > > > > like to hold this patch for now, until we got a clear answer from > > > > our architect. Would you please help revert this patch (the other > > > > patches are safe and can be merged), sorry for the inconvenience. > > > > > > > I modified the subject slightly to be more specific. > > > Adding lkml and x86 list, and a few more people. > > > This commit is also affected, won't compile if we revert the one > > > above. > > > > > > 37c528e... x86/tsc_msr: Fix rdmsr(MSR_PLATFORM_INFO) unsafe warning > > > in KVM guest > > > > Ok, I've rebased tip:x86/timers, it now includes the following > > commits: > > > > ff4c86635ee1 x86/tsc: Enumerate BXT tsc_khz via CPUID > > aa297292d708 x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID > > 02c0cd2dcf7f x86/tsc_msr: Remove irqoff around MSR-based TSC > > enumeration 6fcb41cdaee5 x86/tsc_msr: Add Airmont reference clock > > values 05680e7fa8a4 x86/tsc_msr: Correct Silvermont reference clock > > values 9e0cae9f6227 x86/tsc_msr: Update comments, expand definitions > > 14bb4e34860a x86/tsc_msr: Remove debugging messages > > ba8268330dc1 x86/tsc_msr: Identify Intel-specific code > > fc5f3ac24720 Revert "x86/tsc: Add missing Cherrytrail frequency to the > > table" > > > > Does that work for you? > > > works for me but Yu has to confirm. > Confirmed, thanks! thanks, Yu