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Tue, 22 Oct 2024 06:34:17 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49M6YGsx027941 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2024 06:34:16 GMT Received: from [10.216.44.181] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 21 Oct 2024 23:34:11 -0700 Message-ID: <36bfe493-8a85-4add-93e3-650b002636df@quicinc.com> Date: Tue, 22 Oct 2024 12:04:09 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/6] clk: qcom: Add support for GPU Clock Controller on QCS8300 To: Krzysztof Kozlowski , Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Taniya Das , Jagadeesh Kona , "Satya Priya Kakitapalli" , , , , References: <20241018-qcs8300-mm-patches-v1-0-859095e0776c@quicinc.com> <20241018-qcs8300-mm-patches-v1-2-859095e0776c@quicinc.com> <34216857-170c-45d4-8f6d-987573269215@kernel.org> Content-Language: en-US From: Imran Shaik In-Reply-To: <34216857-170c-45d4-8f6d-987573269215@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _Z9cHtAk172C_5x6AprBo93FeR1XZQOR X-Proofpoint-GUID: _Z9cHtAk172C_5x6AprBo93FeR1XZQOR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 mlxscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1011 malwarescore=0 impostorscore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410220041 On 10/21/2024 8:41 PM, Krzysztof Kozlowski wrote: > On 21/10/2024 12:56, Dmitry Baryshkov wrote: >>>> { } >>>> }; >>>> @@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev) >>>> if (IS_ERR(regmap)) >>>> return PTR_ERR(regmap); >>>> >>>> + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) { >>> >>> Why we cannot use match data? Seeing compatibles in the code is >>> unexpected and does not scale. >> >> Because using match data doesn't scale in such cases. We have been using > > I don't understand how it could not scale. That's the entire point of > match data - scaling. > >> compatibles to patch clock trees for the platforms for quite a while. >> You can see that each of the "tunings" is slightly different. From my > > > You have one driver, where are these tunings which are supposed to be > different? You need here only enum or define, in the simplest choice. > >> point of view, this approach provides a nice balance between having a >> completely duplicate driver and having a driver which self-patches the >> tree. > > How duplicate driver got into this? I don't think we talk about the > same. I meant ID table match data. >> I agree with Dmitry. If I understand correctly, to add match data support, we need to define the gpu_cc_qcs8300_clocks struct by duplicating the entries from gpu_cc_sa8775p_clocks and then adding the additional qcs8300 clocks. The compatible approach is simpler and used across most existing platforms. Thanks, Imran > > Best regards, > Krzysztof >