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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id eo30-20020a056512481e00b0050e7ed9585asm617280lfb.233.2024.01.10.03.00.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Jan 2024 03:00:39 -0800 (PST) Message-ID: <36f9eac0-3086-4d18-9879-02738e99d262@linaro.org> Date: Wed, 10 Jan 2024 12:00:35 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation Content-Language: en-US To: Bibek Kumar Patro , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, dmitry.baryshkov@linaro.org, jsnitsel@redhat.com, quic_bjorande@quicinc.com, mani@kernel.org, quic_eberman@quicinc.com, robdclark@chromium.org, u.kleine-koenig@pengutronix.de, robh@kernel.org, vladimir.oltean@nxp.com, quic_pkondeti@quicinc.com, quic_molvera@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, qipl.kernel.upstream@quicinc.com References: <20240109114220.30243-1-quic_bibekkum@quicinc.com> <20240109114220.30243-2-quic_bibekkum@quicinc.com> From: Konrad Dybcio In-Reply-To: <20240109114220.30243-2-quic_bibekkum@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/9/24 12:42, Bibek Kumar Patro wrote: > Default MMU-500 reset operation disables context caching in > prefetch buffer. It is however expected for context banks using > the ACTLR register to retain their prefetch value during reset > and runtime suspend. > > Replace default MMU-500 reset operation with Qualcomm specific reset > operation which envelope the default reset operation and re-enables > context caching in prefetch buffer for Qualcomm SoCs. > > Signed-off-by: Bibek Kumar Patro > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++-- > 1 file changed, 34 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 549ae4dba3a6..000e207346af 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -14,6 +14,16 @@ > > #define QCOM_DUMMY_VAL -1 > > +/* > + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the > + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch > + * buffer). The remaining bits are implementation defined and vary across > + * SoCs. > + */ > + > +#define CPRE (1 << 1) > +#define CMTLB (1 << 0) > + > static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) > { > return container_of(smmu, struct qcom_smmu, smmu); > @@ -376,11 +386,32 @@ static int qcom_smmu_def_domain_type(struct device *dev) > return match ? IOMMU_DOMAIN_IDENTITY : 0; > } > > +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) > +{ > + int ret; > + u32 val; > + int i; > + > + ret = arm_mmu500_reset(smmu); > + > + if (ret) Weird empty line.. Please remove it in the next revision since you're already going to send a new one.. Reviewed-by: Konrad Dybcio Konrad