From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751668AbdKYRbJ (ORCPT ); Sat, 25 Nov 2017 12:31:09 -0500 Received: from mail-qk0-f196.google.com ([209.85.220.196]:37181 "EHLO mail-qk0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdKYRbH (ORCPT ); Sat, 25 Nov 2017 12:31:07 -0500 X-Google-Smtp-Source: AGs4zMb5wqYyem27qHmQ5IqKBkXa+apIeNuiGxLegfhzOn21j0CXog63jocanhx0pKRfM8dKfxsMVw== From: Nadav Amit Message-Id: <372BBE7D-1397-4EFB-BB60-0638710F11DB@gmail.com> Content-Type: multipart/signed; boundary="Apple-Mail=_180F44C5-8A2E-46EE-9C01-57D6FF334752"; protocol="application/pgp-signature"; micalg=pgp-sha512 Mime-Version: 1.0 (Mac OS X Mail 10.3 \(3273\)) Subject: Re: [PATCH v2 2/2] x86: disable IRQs before changing CR4 Date: Sat, 25 Nov 2017 09:31:03 -0800 In-Reply-To: Cc: LKML , linux-edac@vger.kernel.org, Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tony Luck , Borislav Petkov , Paolo Bonzini , =?utf-8?B?UmFkaW0gS3LEjW3DocWZ?= To: Thomas Gleixner References: <20171125032907.2241-1-namit@vmware.com> <20171125032907.2241-3-namit@vmware.com> <803D7D69-1F01-4CB8-A966-A040F302D1C0@gmail.com> X-Mailer: Apple Mail (2.3273) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Apple-Mail=_180F44C5-8A2E-46EE-9C01-57D6FF334752 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii Thomas Gleixner wrote: > On Sat, 25 Nov 2017, Nadav Amit wrote: >> Thomas Gleixner wrote: >>=20 >>> On Fri, 24 Nov 2017, Nadav Amit wrote: >>>> /* Set in this cpu's CR4. */ >>>> -static inline void cr4_set_bits(unsigned long mask) >>>> +static inline void cr4_set_bits_irqs_off(unsigned long mask) >>>=20 >>> This change is kinda weird. I'd expect that there is a corresponding >>> function cr4_set_bits() which takes care of disabling interrupts. = But there >>> is not. All it does is creating a lot of pointless churn. >>>=20 >>>> static __always_inline void setup_smep(struct cpuinfo_x86 *c) >>>> static __init int setup_disable_smap(char *arg) >>>> static __always_inline void setup_pku(struct cpuinfo_x86 *c) >>>=20 >>> Why are you not doing this at the call site around all calls which = fiddle >>> with cr4, i.e. in identify_cpu() ? >>>=20 >>> identify_cpu() is called from two places: >>>=20 >>> identify_boot_cpu() and identify_secondary_cpu() >>>=20 >>> identify_secondary_cpu is called with interrupts disabled anyway and = there >>> is no reason why we can't enforce interrupts being disabled around >>> identify_cpu() completely. >>>=20 >>> But if we actually do the right thing, i.e. having cr4_set_bit() and >>> cr4_set_bit_irqsoff() all of this churn goes away magically. >>>=20 >>> Then the only place which needs to be changed is the context switch = because >>> here interrupts are already disabled and we really care about = performance. >>>=20 >>>> @@ -293,7 +303,7 @@ void __switch_to_xtra(struct task_struct = *prev_p, struct task_struct *next_p, >>>> } >>>>=20 >>>> if ((tifp ^ tifn) & _TIF_NOTSC) >>>> - cr4_toggle_bits(X86_CR4_TSD); >>>> + cr4_toggle_bits_irqs_off(X86_CR4_TSD); >>=20 >> You make a good point. I will add cr4_set_bit(). I will leave = identify_cpu() >> as is, since it is rather hard to maintain code that enables/disables = irqs >> at one point and rely on these operations at a completely different = place. >> As you said, it is less of an issue once cr4_set_bit() and friends = are >> introduced. >=20 > I fixed that up already as I wanted to have it done, see the tip-bot = mail > in your inbox. Thanks, your changes made it much better. At some point it might be = better to make the MTRR code to use these interfaces too instead of meddling = with CR4 directly. Anyhow, that is a different story. Regards, Nadav --Apple-Mail=_180F44C5-8A2E-46EE-9C01-57D6FF334752 Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE0YCJM4pMIpzxUdmOK4dOkxJsY0AFAloZqNcACgkQK4dOkxJs Y0DECA/9HpNVG0WiXDmY6+VbesNpXYxkGE9kMFyVWXLrbYacykTLj7sw4LFTsbat z07w73tmswu4RmbSD8fxFW5CDOPu+dOJpWPD3EtvbyQi4y2DY9GS3DVnFTYOwplP A5zUckn2Ve01doC/n1Oazy4/pOGBbaq1zifT6PFsXdCpK7R7Cm2mQ2oqysNEpdZB GDwYsqIKSBNqP4Kwz4Qn2AFwSEOVWzLrOxML8CVeR602Yzb8RmwfPvoUA2yvmFFk z2MscnTcCPyFfxq79kD3NKM+4Mnn9TM2jorPpqksAqybeNcDUWluSd5chQdh1FPV rP/vqWGAeePy0Gnifpy8Dk82cKgfIKxlWiWE2HUp/VLGdDe6MRlxtBGWGu/jBRxL DK0SetskIj/mSraLLEd1Dgx6QugGF47to3kFRrx0rxQ03tbFZczgj5BatFK3aWAG TRzcGSe2Q5EnN98KVDng7kD6soWwuxF3J0CBwkIm9N3vdTPrjr8s4x58Xlpyz8i9 WPTPqb0a0R5VhUVNtZkFfqg15/YXDyF0xzDSxvbz69naHlv8/4KYvlHg7lLnQTrI ifLz98s0nAo1VfwiZnRaI4STaHF4Edl5tyDC4vnYGlIZGQS21Fe+rCd+Amg+MMNU j9XDjXmd2YjG0rNf/6EnyB8RN837K73uPjfEA4SbeIWpZY4jnMY= =g7W6 -----END PGP SIGNATURE----- --Apple-Mail=_180F44C5-8A2E-46EE-9C01-57D6FF334752--