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Tue, 20 Oct 2026 21:57:31 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 69L1vUPA006939 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Oct 2026 21:57:30 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Tue, 20 Oct 2026 21:57:30 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Tue, 20 Oct 2026 21:57:30 -0400 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 69L1vHHl029062; Tue, 20 Oct 2026 21:57:20 -0400 From: Jonathan Santos To: , , , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v4 3/9] spi: support simultaneous assertion of multiple CS Date: Tue, 20 Oct 2026 22:57:12 -0300 Message-ID: <372aad8ff5acef8412edef77ab1b7fcce7a902fd.1792435248.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=EvBHPicA c=1 sm=1 tr=0 ts=6ad81c0b cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=gAnH3GRIAAAA:8 a=k-FQ2K6VbMuEqB_s0bsA:9 X-Proofpoint-GUID: xYv2xklP6Ad1dN-kE_RFHu9hquCmRDkK X-Proofpoint-ORIG-GUID: xYv2xklP6Ad1dN-kE_RFHu9hquCmRDkK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAwNyBTYWx0ZWRfXx9jKhT1uM8lo wBqQTOIJWVArlqEBlH7GViIhhVmDYQ0fV8RIcHTq/pqEkapOXYUmI33Rpd3vEjWN04hzYskoH2m Yi2r0zip7UkG95F74BLo435lAjG6PdDB94LRE/10YhRIF+W5Ut05ibuua+75qw7TaILzAIlrqYr IDdLGZ2tJp9FEnpjY4/zxUkW3J7S5a5V3VCP7H5sS9+UePWHRDyNj46KLtbNL/RDeiRWc4Ykftj BNiw1FWG/+/6hbkypHKYhTUQl4d8A4+mfQ8mYvH64OMdKX7D35PybnO0yxPk9nQQrNYfZZNjMN/ pFuUYLUk+8041j2o76VvJ99nwbE2sH/0jM0YHef/SzL6ATeuNBWDAUZ3He1tYPmU4jDR0jDk32p JRRkWt7QoSpXNEsoQ27bw5nlTsYGPlMpgQYj6EyudNRm/DcDnmS2CrgkuRBHFgPdR52hvLaveIr hkp2xRpbGCFSl6wHScA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAwNyBTYWx0ZWRfX0hz40WKSfBch xmMfk5i0Kle21O91K0Q91DBysd8cTf1Oi0dDG0owbXThZtrwvafQ4QfnGymbwHAOwcOgHDAalM8 JHj2ylW9HoaAUiHL6tAoeJcoEEHviO0uNcEXSlei0mfgSvGCyzMK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_04,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 priorityscore=1501 clxscore=1011 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210007 Some SPI controllers allow multiple CS lines to be toggled at the same time. The existing code always used CS index 0 when tracking the last active CS in spi_set_cs(), and unconditionally set cs_index_mask to BIT(0) when parsing DT, both forcing the single CS usage. Modify spi_set_cs() to iterate last_cs[] using each logical CS index instead of always reading index 0. Modify of_spi_parse_dt() to build cs_index_mask from all parsed CS entries when 'spi-cs-composite' is set, so the controller identifies which CS lines belong to a device when asserting them simultaneously as a composite device. Board info, ACPI, and ancillary device paths are not updated here. Board info would require an API change to accept an array of CS values and is left for a follow-up when we have a use case for this. Ancillary devices are by design single-CS, so multi-CS is not a current use case for them. ACPI represents the CS as a 64-bit integer with no established convention for encoding multiple CS indices yet, so any extension there would require a separate specification effort. Signed-off-by: Jonathan Santos --- Changes in v4: * use spi-cs-composite to determine whether to assert all CS lines together, rather than always asserting them together. * Replaced the for-loop to assign the spi->cs_index_mask with "GENMASK(spi->num_chipselect - 1, 0)". Changes in v3: * None. Changes in v2: * Include Summary describing why the other SPI paths were not addressed here. --- drivers/spi/spi.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 5b5b3bc5f0d8..7a0406ec200e 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1278,7 +1278,7 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force) spi->controller->last_cs_index_mask = spi->cs_index_mask; for (idx = 0; idx < SPI_DEVICE_CS_CNT_MAX; idx++) { if (enable && idx < spi->num_chipselect) - spi->controller->last_cs[idx] = spi_get_chipselect(spi, 0); + spi->controller->last_cs[idx] = spi_get_chipselect(spi, idx); else spi->controller->last_cs[idx] = SPI_INVALID_CS; } @@ -2794,8 +2794,19 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, /* * By default spi->chip_select[0] will hold the physical CS number, * so set bit 0 in spi->cs_index_mask. + * + * If "spi-cs-composite" is present, assert all CS lines at once + * so the device acts as a single composite target. */ - spi->cs_index_mask = BIT(0); + if (of_property_read_bool(nc, "spi-cs-composite")) { + if (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS)) { + dev_err(&ctlr->dev, "SPI controller doesn't support multi CS\n"); + return -EINVAL; + } + spi->cs_index_mask = GENMASK(spi->num_chipselect - 1, 0); + } else { + spi->cs_index_mask = BIT(0); + } /* Device speed */ if (!of_property_read_u32(nc, "spi-max-frequency", &value)) -- 2.34.1