From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFA5DC433F5 for ; Tue, 7 Sep 2021 09:10:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB69361106 for ; Tue, 7 Sep 2021 09:10:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245065AbhIGJLU (ORCPT ); Tue, 7 Sep 2021 05:11:20 -0400 Received: from foss.arm.com ([217.140.110.172]:33528 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244782AbhIGJLQ (ORCPT ); Tue, 7 Sep 2021 05:11:16 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FDCD31B; Tue, 7 Sep 2021 02:10:10 -0700 (PDT) Received: from [10.57.94.84] (unknown [10.57.94.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 434273F766; Tue, 7 Sep 2021 02:10:08 -0700 (PDT) Subject: Re: [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode To: Linu Cherian Cc: linux-arm-kernel , Mark Rutland , maz@kernel.org, Anshuman Khandual , catalin.marinas@arm.com, Coresight ML , linux-kernel@vger.kernel.org, james.morse@arm.com, Will Deacon , Mike Leach , Linu Cherian References: <20210728135217.591173-1-suzuki.poulose@arm.com> <20210728135217.591173-8-suzuki.poulose@arm.com> From: Suzuki K Poulose Message-ID: <3731f9a8-2923-8586-4adc-da3550a6c55a@arm.com> Date: Tue, 7 Sep 2021 10:10:06 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/08/2021 13:44, Linu Cherian wrote: > Hi Suzuki, > > On Wed, Jul 28, 2021 at 7:23 PM Suzuki K Poulose wrote: >> >> Arm Neoverse-N2 and the Cortex-A710 cores are affected >> by a CPU erratum where the TRBE will overwrite the trace buffer >> in FILL mode. The TRBE doesn't stop (as expected in FILL mode) >> when it reaches the limit and wraps to the base to continue >> writing upto 3 cache lines. This will overwrite any trace that >> was written previously. >> >> Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum >> (#2119858) to the detection logic. >> >> This will be used by the TRBE driver in later patches to work >> around the issue. The detection has been kept with the core >> arm64 errata framework list to make sure : >> - We don't duplicate the framework in TRBE driver >> - The errata detection is advertised like the rest >> of the CPU errata. >> >> Note that the Kconfig entries will be added after we have added >> the work around in the TRBE driver, which depends on the cpucap >> from here. >> >> Cc: Will Deacon >> Cc: Mark Rutland >> Cc: Anshuman Khandual >> Cc: Catalin Marinas >> Cc: Mathieu Poirier >> Cc: Mike Leach >> cc: Leo Yan >> Signed-off-by: Suzuki K Poulose >> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps >> index 49305c2e6dfd..1ccb92165bd8 100644 >> --- a/arch/arm64/tools/cpucaps >> +++ b/arch/arm64/tools/cpucaps >> @@ -53,6 +53,7 @@ WORKAROUND_1418040 >> WORKAROUND_1463225 >> WORKAROUND_1508412 >> WORKAROUND_1542419 >> +WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> WORKAROUND_CAVIUM_23154 >> WORKAROUND_CAVIUM_27456 >> WORKAROUND_CAVIUM_30115 > > We need to keep this list sorted ? Not necessary, anymore. For a given kernel the numbers are autogenerated by the script. See arch/arm64/tools/gen-cpucaps.awk Suzuki