Re: [PATCH 1/5] net: cadence: macb: Set upper 32bits of DMA ring buffer

[Nicolas Ferre <nicolas.ferre@microchip.com>]

On 15/08/2025 at 15:59, Stanimir Varbanov wrote:
> In case of rx queue reset and 64bit capable hardware, set the upper
> 32bits of DMA ring buffer address.

Very nice finding! Thanks.

> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

A "Fixes" tag might be interesting here.

> ---
>   drivers/net/ethernet/cadence/macb_main.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index ce95fad8cedd..41c0cbb5262e 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
> 
>                  macb_init_rx_ring(queue);
>                  queue_writel(queue, RBQP, queue->rx_ring_dma);

For the sake of consistency, I would add lower_32_bits() to this call, 
as I see it for each use of RBQP or TBQP.

> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> +               if (bp->hw_dma_cap & HW_DMA_CAP_64B)
> +                       macb_writel(bp, RBQPH,
> +                                   upper_32_bits(queue->rx_ring_dma));
> +#endif
> 
>                  macb_writel(bp, NCR, ctrl | MACB_BIT(RE));

Best regards,
   Nicolas