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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4394127afcbsm45103195e9.23.2025.02.10.06.38.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 06:39:00 -0800 (PST) Message-ID: <374d3b07-e16c-4468-828a-a2a542cd88ac@rivosinc.com> Date: Mon, 10 Feb 2025 15:38:58 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yixun Lan , Longbin Li , Jesse Taube , Yong-Xuan Wang , Samuel Holland , Krzysztof Kozlowski , Evan Green , Andrew Jones , Alexandre Ghiti , Andy Chiu , Charlie Jenkins , Conor Dooley , Rob Herring , Albert Ou , Palmer Dabbelt , Paul Walmsley , Jonathan Corbet , Chen Wang , Inochi Amaoto References: <20241206055829.1059293-1-inochiama@gmail.com> <20241206055829.1059293-3-inochiama@gmail.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <20241206055829.1059293-3-inochiama@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06/12/2024 06:58, Inochi Amaoto wrote: > Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which > were ratified in 4dc23d62 ("Added Chapter title to BF16") of > the riscv-isa-manual. > > Signed-off-by: Inochi Amaoto > --- > arch/riscv/include/asm/hwcap.h | 3 +++ > arch/riscv/kernel/cpufeature.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 869da082252a..14cc29f2a723 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -100,6 +100,9 @@ > #define RISCV_ISA_EXT_ZICCRSE 91 > #define RISCV_ISA_EXT_SVADE 92 > #define RISCV_ISA_EXT_SVADU 93 > +#define RISCV_ISA_EXT_ZFBFMIN 94 > +#define RISCV_ISA_EXT_ZVFBFMIN 95 > +#define RISCV_ISA_EXT_ZVFBFWMA 96 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c0916ed318c2..5cfcab139568 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -341,6 +341,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN), Hi Inochi, You could add a validation callback to that extension: static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) return 0; return -EPROBE_DEFER; } ... __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends), But I'm ok with the current state of that patch since I have the same thing coming for other extensions as well. So with or without my previous comment fixed: Reviewed-by: Clément Léger Thanks, Clément > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), > __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), > @@ -373,6 +374,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), > __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), > __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), > + __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN), > + __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA), > __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), > __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), > __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),