From: "Csókás Bence" <csokas.bence@prolan.hu>
To: Dipen Patel <dipenp@nvidia.com>, <linux-iio@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<timestamp@lists.linux.dev>
Cc: William Breathitt Gray <wbg@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Lars-Peter Clausen <lars@metafoo.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [Q] Frequency & duty cycle measurement?
Date: Wed, 26 Feb 2025 14:56:56 +0100 [thread overview]
Message-ID: <3758bdc7-2eb3-4e42-845a-8ecb1103d4f1@prolan.hu> (raw)
In-Reply-To: <7b6505ca-6082-4644-be4d-6e1372c183b7@nvidia.com>
Hi,
On 2025. 02. 19. 23:32, Dipen Patel wrote:
> On 1/21/25 7:19 AM, Csókás Bence wrote:
>> he hardware is capable of taking a snapshot of the timer value into another
>> dedicated register pair (RA, RB) on the rising/falling edges, and a small
>> `devmem`-based userspace utility was created as a working PoC
> I am late to the party :) Seems above statement looks lot like what HTE
> subsystem is doing. Right now, only userspace path is through the gpiolib
> due to usage that time was limited to GPIOs. However, we can extend HTE to meet
> this scenario.
Yes, I had the same impression. But since there was already a driver for
this block in the counter subsystem, it was easier to extend that to our
use case.
> Thanks,
> Best Regards,
> Dipen Patel
>
Bence
prev parent reply other threads:[~2025-02-26 13:56 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 15:19 Csókás Bence
2025-01-21 17:45 ` David Lechner
2025-01-27 15:00 ` William Breathitt Gray
2025-01-30 13:59 ` Csókás Bence
2025-02-04 23:37 ` William Breathitt Gray
2025-02-05 9:30 ` Csókás Bence
2025-02-05 9:58 ` Csókás Bence
2025-02-19 22:32 ` Dipen Patel
2025-02-26 13:56 ` Csókás Bence [this message]
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