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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=Z+PsHGRA c=1 sm=1 tr=0 ts=68650e14 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=z-AMgQe07C8pQQwPwfQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA4NyBTYWx0ZWRfX9mbpLt0tjQ/c CHmfUPhEXSAmgNiehjovpqFr7RLOK5TppBtBQafa8F4nCrqiejfW6mhWhx7JKpbYbinrI8WZ9wK qlRe7jwI/3BtoFaXoCtgI64baP/OTvn9c52hI4tHum/3ZL2taO2KkeWJZvDduZcvwb1HdIuU4i3 Fu0LGvqP4wgAzvinFT5zjxAFVieu0GX+WtsGvfckIXeOv8lhaHenouPCZ7ruxsgIrF6Og/fKJmk IQFJiHgsIBKdmUaQJj97aztPFhRPN027nVLWQqGMAmcaQft7geqwcAkPL11FJUWjmL3n14l9B/J CCs5pZAi/V4X1j/ifWVBQ1I7I9Go/3AAw3nKWPJEGSCFTDIb0JaC9fsD7szMPlxc6x9OlHhv539 BZm3n10iRN0zXeFXKsV3fb5MvM5vuA7XE0zE115ul6/dL5D+4ON3V6qSY/YU0GSgXwvUZY7N X-Proofpoint-GUID: jRsuH2DQWMkKKQ4Qg49EhYjf9lVribYR X-Proofpoint-ORIG-GUID: jRsuH2DQWMkKKQ4Qg49EhYjf9lVribYR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 mlxlogscore=810 spamscore=0 adultscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020087 On 7/2/2025 3:49 PM, Krzysztof Kozlowski wrote: > On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: >> IMEM is present in the Qualcomm's IPQ SoCs as well. Document the same. >> >> Signed-off-by: Kathiravan Thirumoorthy >> --- >> Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ >> 1 file changed, 6 insertions(+) > > Where is the changelog? This is not a v1. This is the v1. The series[1] I pointed out describes only for the IPQ5424 SoC. Since I have added few more SoCs, thought v1 is the appropriate numbering. [1] https://lore.kernel.org/linux-arm-msm/20250610-wdt_reset_reason-v5-0-2d2835160ab5@oss.qualcomm.com/ > >> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >> index 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda 100644 >> --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >> +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >> @@ -18,6 +18,12 @@ properties: >> items: >> - enum: >> - qcom,apq8064-imem >> + - qcom,ipq8074-imem >> + - qcom,ipq6018-imem >> + - qcom,ipq5018-imem >> + - qcom,ipq9574-imem >> + - qcom,ipq5332-imem >> + - qcom,ipq5424-imem > Random order, no, follow existing style. This applies for every qcom > binding and you received such feedbacks in the past. Apologies — I arranged them based on the evolutionary order of SoCs. I’ll correct this in v2 and ensure it’s handled properly in the future. > > Best regards, > Krzysztof