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cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4995.14; Wed, 16 Feb 2022 05:45:15 +0000 Received: from CWLP123MB5572.GBRP123.PROD.OUTLOOK.COM ([fe80::6dad:8602:45c5:6747]) by CWLP123MB5572.GBRP123.PROD.OUTLOOK.COM ([fe80::6dad:8602:45c5:6747%8]) with mapi id 15.20.4995.016; Wed, 16 Feb 2022 05:45:15 +0000 Message-ID: <378824ab-3cc9-dcf5-b9ea-5e49b57792a6@camlingroup.com> Date: Wed, 16 Feb 2022 06:45:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH] serial: imx: leave IRTS disabled if using modem-control CTS To: Tim Harvey CC: Greg Kroah-Hartman , Jiri Slaby , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-serial@vger.kernel.org, Linux ARM Mailing List , open list , Richard Genoud , Sergey Organov , =?UTF-8?Q?Tomasz_Mo=c5=84?= References: <20220214213020.685-1-tharvey@gateworks.com> <9d5cff18-5493-f6dd-4bd6-9bafa2a503a7@camlingroup.com> From: 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X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2022 05:45:15.6474 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: fd4b1729-b18d-46d2-9ba0-2717b852b252 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OjqG8WIS9sWPmIjdMTInneOI5Dm7cjIQgxZrewHgYzMQvPNgOL/vBYj+idvm90tjZ551Y+3no9NWJXDGKlwdfiVvihUhfJI8Tk0DpcnSKQk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: LO4P123MB6370 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUK97A341 smtp.mailfrom=tomasz.mon@camlingroup.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: camlingroup.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15.02.2022 18:26, Tim Harvey wrote: > On Mon, Feb 14, 2022 at 10:03 PM Tomasz Mo=C5=84 wrote: >> This hardware flow control sounds quite limited. Once CTS becomes >> inactive, the transmitter will still output all characters from TxFIFO. >> Transmitting whole TxFIFO already sounds quite bad, but that's the best >> case scenario where gpio interrupt is handled right away without any >> delay (so more than TxFIFO characters can actually be transmitted). >> >> Does the internal RTS default to inactive when it's not pinmuxed to the >> actual pin? If so, then controlling UCR2_IRTS based on CTS gpio could >> halt the transmission when the TxFIFO is not empty. >>> I agree that the increased latency makes using a GPIO for CTS > (software controlled) not as good as one pinmuxed into the UART block > directly (hardware controlled) but without this patch GPIO for CTS > does not work at all because the internal RTS defaults to inactive > when its not pinmuxed. For many applications the latency is not an > issue. I think I didn't write the message clear enough. I agree, that the GPIO handling time is something the user has to accept. Usually this part alone is not that bad though, as many receivers are capable of receiving more than one character after deasserting their RTS output (transmitter CTS input). The general expectation is that the transmitter will output maximum one more character *after* CTS GPIO change is handled by software. This is not the case with current version of the patch. With current version of the patch, after CTS GPIO handler finishes, the UART will continue to transmit up to 32 characters if not using DMA. When DMA is active it is much worse, as it will keep transmitting all data already submitted to dmaengine. As the internal RTS defaults to inactive when its not pinmuxed, the software is able to freeze the TxFIFO (and thus DMA if enabled). To freeze TxFIFO when using CTS GPIO, the software has to clear IRTS bit in UCR2 register. Setting IRTS will thaw the TxFIFO. Best Regards, Tomasz Mon