From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B96DC426685 for ; Wed, 27 May 2026 14:50:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779893417; cv=none; b=mY+KeSwrujrWghfv5WunV5wNnjwXElYiLizTxHOKsVtbKkwSkLf4RVV4JpIVNekeEPzwlA6663xLsI7YLhfDaEzquivs9j6puO7oBEOgg4Jo0h6P13kBPjnKNKeR3KtHh9Q6kbZH03LlePobFm3H485hMxHvyJBn6VkiMbafd3M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779893417; c=relaxed/simple; bh=7dm+IcWy2GbjTqM6dc0YYdnL44VCkB0uXF4KC7zHDBs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rWIzF2Ik4KoElp8a9Wg3OeDzpSk3xlkf+DHL5UgOmXXxcEYOu90y3f8RGMqQEs8PuRXG/1OdksJDAb63GEjwrEdvBAIXhgCthopZEYE7lQON1DN8SOhaiVLHmgYgeShl7nfvyfqXStNIrm7+/mdtUOJ0CQqgjtUJRdQxMtsbHiU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=GBpovObz; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="GBpovObz" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C3A427DC; Wed, 27 May 2026 07:50:09 -0700 (PDT) Received: from [10.1.36.149] (XHFQ2J9959.cambridge.arm.com [10.1.36.149]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5F8EF3F905; Wed, 27 May 2026 07:50:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1779893414; bh=7dm+IcWy2GbjTqM6dc0YYdnL44VCkB0uXF4KC7zHDBs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=GBpovObzipwzMuVhUKwdxq0xb+qG6dGlZTlWziOa4PzM2Gtbk4H7X2unRbm4KEED0 Hd2z57o03z6Z1lLdqtPm3oCLclksKwXjm4Z80jBBC0Cj5c+9CnCZ3XAee84XOVk6JI nKXDh2ckmGCYNmYtmQistQyImY8AIfOaJgnlzp+g= Message-ID: <37917d56-ae26-4789-ac4c-15f8ee12398b@arm.com> Date: Wed, 27 May 2026 15:50:10 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC V2 13/14] arm64/mm: Add an abstraction level for tlbi_op Content-Language: en-GB To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Stoakes , Andrew Morton , David Hildenbrand , Mike Rapoport , Linu Cherian , Usama Arif , linux-kernel@vger.kernel.org, linux-mm@kvack.org References: <20260513044547.4128549-1-anshuman.khandual@arm.com> <20260513044547.4128549-14-anshuman.khandual@arm.com> From: Ryan Roberts In-Reply-To: <20260513044547.4128549-14-anshuman.khandual@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 13/05/2026 05:45, Anshuman Khandual wrote: > From: Linu Cherian > > With FEAT_D128, a new instruction aka TLBIP is being introduced for the TLB > range operations which has an argument size of 128 bit. nit: TLB range operations -> TLBI-by-range operations ? > > Add an abstraction level to void (*tlbi_op)(u64 arg) helpers to support the > D128 variations when applicable. > > No functional changes are introduced with this patch. > > Signed-off-by: Linu Cherian > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/tlbflush.h | 70 ++++++++++++++++--------------- > 1 file changed, 37 insertions(+), 33 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index c0bf5b398041..361d74ef8016 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -162,49 +162,53 @@ static inline void sme_dvmsync_batch(struct arch_tlbflush_unmap_batch *batch) > > #define TLBI_TTL_UNKNOWN INT_MAX > > -typedef void (*tlbi_op)(u64 arg); > +typedef u64 tlbi_args_t; nit: tlbi_args_t -> tlbi_arg_t ? > +#define __tlbi_wrapper(op, arg) __tlbi(op, arg) > +#define __tlbi_user_wrapper(op, arg) __tlbi_user(op, arg) I'm not a huge fan of these, but I can see why you did it this way. Thanks, Ryan > > -static __always_inline void vae1is(u64 arg) > +typedef void (*tlbi_op)(tlbi_args_t arg); > + > +static __always_inline void vae1is(tlbi_args_t arg) > { > - __tlbi(vae1is, arg); > - __tlbi_user(vae1is, arg); > + __tlbi_wrapper(vae1is, arg); > + __tlbi_user_wrapper(vae1is, arg); > } > > -static __always_inline void vae2is(u64 arg) > +static __always_inline void vae2is(tlbi_args_t arg) > { > - __tlbi(vae2is, arg); > + __tlbi_wrapper(vae2is, arg); > } > > -static __always_inline void vale1(u64 arg) > +static __always_inline void vale1(tlbi_args_t arg) > { > - __tlbi(vale1, arg); > - __tlbi_user(vale1, arg); > + __tlbi_wrapper(vale1, arg); > + __tlbi_user_wrapper(vale1, arg); > } > > -static __always_inline void vale1is(u64 arg) > +static __always_inline void vale1is(tlbi_args_t arg) > { > - __tlbi(vale1is, arg); > - __tlbi_user(vale1is, arg); > + __tlbi_wrapper(vale1is, arg); > + __tlbi_user_wrapper(vale1is, arg); > } > > -static __always_inline void vale2is(u64 arg) > +static __always_inline void vale2is(tlbi_args_t arg) > { > - __tlbi(vale2is, arg); > + __tlbi_wrapper(vale2is, arg); > } > > -static __always_inline void vaale1is(u64 arg) > +static __always_inline void vaale1is(tlbi_args_t arg) > { > - __tlbi(vaale1is, arg); > + __tlbi_wrapper(vaale1is, arg); > } > > -static __always_inline void ipas2e1(u64 arg) > +static __always_inline void ipas2e1(tlbi_args_t arg) > { > - __tlbi(ipas2e1, arg); > + __tlbi_wrapper(ipas2e1, arg); > } > > -static __always_inline void ipas2e1is(u64 arg) > +static __always_inline void ipas2e1is(tlbi_args_t arg) > { > - __tlbi(ipas2e1is, arg); > + __tlbi_wrapper(ipas2e1is, arg); > } > > static __always_inline void __tlbi_level_asid(tlbi_op op, u64 addr, u32 level, > @@ -475,32 +479,32 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) > * operations can only span an even number of pages. We save this for last to > * ensure 64KB start alignment is maintained for the LPA2 case. > */ > -static __always_inline void rvae1is(u64 arg) > +static __always_inline void rvae1is(tlbi_args_t arg) > { > - __tlbi(rvae1is, arg); > - __tlbi_user(rvae1is, arg); > + __tlbi_wrapper(rvae1is, arg); > + __tlbi_user_wrapper(rvae1is, arg); > } > > -static __always_inline void rvale1(u64 arg) > +static __always_inline void rvale1(tlbi_args_t arg) > { > - __tlbi(rvale1, arg); > - __tlbi_user(rvale1, arg); > + __tlbi_wrapper(rvale1, arg); > + __tlbi_user_wrapper(rvale1, arg); > } > > -static __always_inline void rvale1is(u64 arg) > +static __always_inline void rvale1is(tlbi_args_t arg) > { > - __tlbi(rvale1is, arg); > - __tlbi_user(rvale1is, arg); > + __tlbi_wrapper(rvale1is, arg); > + __tlbi_user_wrapper(rvale1is, arg); > } > > -static __always_inline void rvaale1is(u64 arg) > +static __always_inline void rvaale1is(tlbi_args_t arg) > { > - __tlbi(rvaale1is, arg); > + __tlbi_wrapper(rvaale1is, arg); > } > > -static __always_inline void ripas2e1is(u64 arg) > +static __always_inline void ripas2e1is(tlbi_args_t arg) > { > - __tlbi(ripas2e1is, arg); > + __tlbi_wrapper(ripas2e1is, arg); > } > > static __always_inline void __tlbi_range(tlbi_op op, u64 addr,