From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Zide Chen <zide.chen@intel.com>,
Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: kvm@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
Jim Mattson <jmattson@google.com>,
Stephane Eranian <eranian@google.com>,
linux-kernel@vger.kernel.org, Mingwei Zhang <mizhang@google.com>,
Das Sandipan <Sandipan.Das@amd.com>,
Shukla Manali <Manali.Shukla@amd.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: Re: [PATCH v2 03/16] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu
Date: Tue, 1 Sep 2026 10:17:38 +0800 [thread overview]
Message-ID: <37a416c8-ccd9-4f57-a21f-1e663a8e9fca@linux.intel.com> (raw)
In-Reply-To: <20260827223755.143247-4-zide.chen@intel.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
On 8/28/2026 6:37 AM, Zide Chen wrote:
> This field stores the bits that are reserved in guest IA32_PERFEVTSELx
> MSRs. Rename it to eventsel_rsvd to better reflect its purpose and to
> align with other field names in struct kvm_pmu.
>
> Opportunistically, replace the magic number 0xffffffff00200000ull with
> macros.
>
> No functional change intended.
>
> Suggested-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
> v2:
> - Replace magic numbers in AMD pmu->eventsel_rsvd.
> ---
> arch/x86/include/asm/kvm_host.h | 2 +-
> arch/x86/kvm/pmu.c | 6 +++++-
> arch/x86/kvm/svm/pmu.c | 12 +++++++++---
> arch/x86/kvm/vmx/pmu_intel.c | 12 ++++++------
> 4 files changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index e473796da7d9..90d80483df7f 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -580,7 +580,7 @@ struct kvm_pmu {
> u64 counter_bitmask[2];
> u64 global_ctrl_rsvd;
> u64 global_status_rsvd;
> - u64 reserved_bits;
> + u64 eventsel_rsvd;
> u64 raw_event_mask;
> struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS];
> struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS];
> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
> index 8f2effee3b7b..964e74bdaaa7 100644
> --- a/arch/x86/kvm/pmu.c
> +++ b/arch/x86/kvm/pmu.c
> @@ -989,7 +989,11 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
> pmu->nr_arch_fixed_counters = 0;
> pmu->counter_bitmask[KVM_PMC_GP] = 0;
> pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
> - pmu->reserved_bits = 0xffffffff00200000ull;
> + /*
> + * KVM is not able to emulate the AnyThread bit due to cross-VM
> + * information leakage on SMT cores.
> + */
> + pmu->eventsel_rsvd = GENMASK_ULL(63, 32) | ARCH_PERFMON_EVENTSEL_ANY;
> pmu->raw_event_mask = X86_RAW_EVENT_MASK;
> pmu->global_ctrl_rsvd = ~0ull;
> pmu->global_status_rsvd = ~0ull;
> diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
> index c18286545a7a..52224872e0d4 100644
> --- a/arch/x86/kvm/svm/pmu.c
> +++ b/arch/x86/kvm/svm/pmu.c
> @@ -163,7 +163,7 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> /* MSR_EVNTSELn */
> pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
> if (pmc) {
> - data &= ~pmu->reserved_bits;
> + data &= ~pmu->eventsel_rsvd;
> if (data != pmc->eventsel) {
> pmc->eventsel = data;
> pmc->eventsel_hw = (data & ~AMD64_EVENTSEL_HOSTONLY) |
> @@ -214,9 +214,15 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
>
> pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1;
>
> - pmu->reserved_bits = 0xfffffff000280000ull;
> + /*
> + * AMD PerfEvtSeln registers do not support PinControl, and KVM does
> + * not emulate AnyThread due to cross-VM information leakage on SMT
> + * cores (as on the Intel side).
> + */
> + pmu->eventsel_rsvd = GENMASK_ULL(63, 36) | ARCH_PERFMON_EVENTSEL_PIN_CONTROL |
> + ARCH_PERFMON_EVENTSEL_ANY;
> if (guest_cpu_cap_has(vcpu, X86_FEATURE_SVM) && kvm_vcpu_has_mediated_pmu(vcpu))
> - pmu->reserved_bits &= ~AMD64_EVENTSEL_HOST_GUEST_MASK;
> + pmu->eventsel_rsvd &= ~AMD64_EVENTSEL_HOST_GUEST_MASK;
>
> pmu->raw_event_mask = AMD64_RAW_EVENT_MASK;
> /* not applicable to AMD; but clean them to prevent any fall out */
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 322a3ad580dd..11c9161dc853 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -385,7 +385,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> struct kvm_pmc *pmc;
> u32 msr = msr_info->index;
> u64 data = msr_info->data;
> - u64 reserved_bits, diff;
> + u64 eventsel_rsvd, diff;
>
> switch (msr) {
> case MSR_CORE_PERF_FIXED_CTR_CTRL:
> @@ -433,11 +433,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> pmc_write_counter(pmc, data);
> break;
> } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
> - reserved_bits = pmu->reserved_bits;
> + eventsel_rsvd = pmu->eventsel_rsvd;
> if ((pmc->idx == 2) &&
> (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED))
> - reserved_bits ^= HSW_IN_TX_CHECKPOINTED;
> - if (data & reserved_bits)
> + eventsel_rsvd ^= HSW_IN_TX_CHECKPOINTED;
> + if (data & eventsel_rsvd)
> return 1;
>
> if (data != pmc->eventsel) {
> @@ -545,7 +545,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
> if (entry &&
> (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
> (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) {
> - pmu->reserved_bits ^= HSW_IN_TX;
> + pmu->eventsel_rsvd ^= HSW_IN_TX;
> pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
> }
>
> @@ -584,7 +584,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
> if (perf_capabilities & PERF_CAP_PEBS_FORMAT) {
> if (perf_capabilities & PERF_CAP_PEBS_BASELINE) {
> pmu->pebs_enable_rsvd = counter_rsvd;
> - pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
> + pmu->eventsel_rsvd &= ~ICL_EVENTSEL_ADAPTIVE;
> pmu->pebs_data_cfg_rsvd = ~0xff00000full;
> intel_pmu_enable_fixed_counter_bits(pmu, ICL_FIXED_0_ADAPTIVE);
> } else {
next prev parent reply other threads:[~2026-09-01 2:17 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 22:37 [PATCH] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Zide Chen
2026-08-27 22:37 ` [PATCH v2 01/16] KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions Zide Chen
2026-09-01 2:07 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 02/16] KVM: x86/pmu: Rename all_valid_pmc_idx to pmc_exists Zide Chen
2026-09-01 2:09 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 03/16] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu Zide Chen
2026-09-01 2:17 ` Mi, Dapeng [this message]
2026-08-27 22:37 ` [PATCH v2 04/16] KVM: x86/pmu: Gate BUFFER_OVF reserved bit on guest DS Zide Chen
2026-09-01 2:30 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 05/16] KVM: x86/pmu: Add PMC bitmap accessor helpers Zide Chen
2026-09-01 2:43 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 06/16] KVM: x86/pmu: Drop nr_arch_{gp,fixed}_counters from kvm_pmu Zide Chen
2026-09-01 3:07 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 07/16] KVM: x86/pmu: Expose kvm_host_pmu to vendor modules Zide Chen
2026-09-01 3:08 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 08/16] perf/x86: Plumb counter bitmap from x86_pmu to x86_pmu_cap Zide Chen
2026-08-27 22:37 ` [PATCH v2 09/16] KVM: x86/pmu: Switch to bitmask-based KVM PMU capabilities Zide Chen
2026-09-01 3:32 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 10/16] perf/x86: Remove num_counters_{gp,fixed} from x86_pmu_capability Zide Chen
2026-08-27 22:37 ` [PATCH v2 11/16] KVM: x86/pmu: Emulate the GLOBAL_STATUS_SET and GLOBAL_INUSE MSRs Zide Chen
2026-09-01 6:45 ` Mi, Dapeng
2026-09-01 14:20 ` Chen, Zide
2026-09-02 0:44 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 12/16] KVM: x86/pmu: Populate CPUID.0AH:ECX fixed-counter bitmap Zide Chen
2026-09-01 6:50 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 13/16] KVM: x86/pmu: Factor out fixed counter control bit calculation Zide Chen
2026-09-01 6:57 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 14/16] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set Zide Chen
2026-09-01 8:01 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 15/16] KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts Zide Chen
2026-08-27 22:37 ` [PATCH v2 16/16] KVM: selftests: Support fixed counters bitmap in pmu_counters_test Zide Chen
2026-08-29 9:30 ` [PATCH] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Peter Zijlstra
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