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Mon, 31 Aug 2026 17:34:15 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v3 10/13] iommu/arm-smmu-v3: Allocate IOPF queue for ARM_SMMU_FEAT_PRI Date: Mon, 31 Aug 2026 17:33:35 -0700 Message-ID: <37a4e140ae26b1f58a08b9274937dcc9fa1e5e57.1788222486.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|SA3PR12MB8048:EE_ X-MS-Office365-Filtering-Correlation-Id: f9c88e15-ae77-4444-4f16-08df07c0cf10 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|82310400026|1800799024|376014|7416014|18002099003|22082099003|56012099006|11063799006|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2nxLQOhKrmfbuE1O/bvBEyrtLZix2uP2PP49Is+yyaAtPTAowV5i/tT2xi4XsITRgX8Ms7tftuViaxfV1WkPGMXSR8AHwzVbB8Itsjb3bYpCXIoe+Ak5YsQ8dPvs8lBZ/FtA+LvlBc+Asjscu9rEjEagzYcWcwrtlCAk3tIqzeuArRkRoBV3qxYG31psFlk6Qj5HcqXUjUsTtpL7guSgCBBWl9JY0hRK31DreMFqBOoYgHhr2kfSc6sQFdncoIR4V6FA+TTAmG8VeQw5GhToAaO1JwbdUB8ywA7jREaDTxZ8/cOERjH3WFfNO06CNPwth3gD6wZ79nBHYUgp47VccHVd7HRjhA7CWeM1WR8EyNG/cEuqicqsdnrCsSEghYhOVNxyH0HlahdUjeOV939q4odTf/tEBkeM7m8nOj3hdBW0JuufAQkVkBSZz7C9AvE/ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2026 00:34:39.7393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9c88e15-ae77-4444-4f16-08df07c0cf10 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8048 After the previous change drops the FEAT_SVA gate, arm_smmu_init_queues() allocates smmu->evtq.iopf when the SMMU advertises FEAT_STALLS. PRI support is being added on top of the IOPF infrastructure, so extend the allocation condition to cover SMMUs that advertise FEAT_PRI without FEAT_STALLS. Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 502b5c7673bc9..47c95b691503b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4741,7 +4741,7 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (ret) return ret; - if (smmu->features & ARM_SMMU_FEAT_STALLS) { + if (smmu->features & (ARM_SMMU_FEAT_STALLS | ARM_SMMU_FEAT_PRI)) { smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); if (!smmu->evtq.iopf) return -ENOMEM; -- 2.43.0