From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6E18A4F3ED4; Fri, 18 Sep 2026 15:56:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789746985; cv=none; b=IhadfvHHnbxhW5gQ1QEhuw4I8VD9E5fSWWtHxrtdW1FK8WOmZoH5tLaSPT/In+9Gq0Cbq8W5AtFCaj4pbboiR4devJXMAWidHxquqx0XCWa6ZWUD9m/7kNc06xlo+60muRNl0cFSb0UeHPd/0KTKV/hyHMdNXoJ0u/iuJcJ4XxQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789746985; c=relaxed/simple; bh=Yztiuro1Xc4OykaRC7nI2YhmfOG7q71r/xjUWYC+jiY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rzbbxZPGDDOjzTXF3sOBdiJhij436FvUyrTZwLC5ZCheMnFh+efnjsA+oqqsIqYEVMzpdAzDAZAWRVQLU5h386kXChpk5d0XY5B7gbNNKwsCdj6Q8gH2S5NHefS8tM+xEgE5lxNj4aFgOZkYqqzuKDk6oId2FXaLZSJaoxAV8ZA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=k8+yX0WZ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="k8+yX0WZ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F24BC168F; Fri, 18 Sep 2026 08:56:18 -0700 (PDT) Received: from [10.57.83.108] (unknown [10.57.83.108]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D24E43F7B4; Fri, 18 Sep 2026 08:56:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789746982; bh=Yztiuro1Xc4OykaRC7nI2YhmfOG7q71r/xjUWYC+jiY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=k8+yX0WZ+rqA/zHh0tPVeR+rCnkkhVppK+TFsnAsx1MVJp9p/INl8Xqdh1PFciqLa Ht6MB/DHCzgmdORKU98cHJb5LEiEMSNgI53Sl4eu8dgPwvgZaI1gJ2AGYSnqO9pgbW 3zEuzJlYEW4yLfB4bv2Ny6h1LJ1ATOXA1EjmCQik= Message-ID: <37bb7c39-f16b-494a-ab96-771b2d4f6b85@arm.com> Date: Fri, 18 Sep 2026 16:56:17 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/6] arm64: convert between HW PTEs and SW PTE values To: Muhammad Usama Anjum , Catalin Marinas , Will Deacon , Mark Rutland , Ard Biesheuvel , Ilias Apalodimas , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Vincenzo Frascino , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org References: <20260914-pte0_arm-v1-0-bb53b663e396@arm.com> <20260914-pte0_arm-v1-3-bb53b663e396@arm.com> From: Ryan Roberts Content-Language: en-GB In-Reply-To: <20260914-pte0_arm-v1-3-bb53b663e396@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 14/09/2026 14:51, Muhammad Usama Anjum wrote: > __ptep_get() returns a SW PTE value, and __set_pte_nosync() accepts one. > When HW PTEs use a distinct hw_pte_t, directly reading or writing *ptep > as a SW PTE value no longer satisfies those interfaces. > > Use __pte_from_hw after READ_ONCE() to obtain a SW PTE value and add > __hw_pte before WRITE_ONCE() to form an HW PTE. > > Define __hw_pte for both the wrapper and alias configurations so the > same accessor code works in either case. > > Signed-off-by: Muhammad Usama Anjum > --- > arch/arm64/include/asm/pgtable.h | 4 ++-- > include/linux/pgtable_types.h | 2 ++ > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index 4768ec59de555..67c4a6179e154 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -360,7 +360,7 @@ static inline pte_t pte_clear_uffd(pte_t pte) > > static inline void __set_pte_nosync(hw_pte_t *ptep, pte_t pte) > { > - WRITE_ONCE(*ptep, pte); > + WRITE_ONCE(*ptep, __hw_pte(pte)); > } > > static inline void __set_pte_complete(pte_t pte) > @@ -381,7 +381,7 @@ static inline void __set_pte(hw_pte_t *ptep, pte_t pte) > > static inline pte_t __ptep_get(hw_pte_t *ptep) > { > - return READ_ONCE(*ptep); > + return __pte_from_hw(READ_ONCE(*ptep)); > } > > extern void __sync_icache_dcache(pte_t pteval); > diff --git a/include/linux/pgtable_types.h b/include/linux/pgtable_types.h > index ee4eace5c3e1c..b5862a16aa497 100644 > --- a/include/linux/pgtable_types.h > +++ b/include/linux/pgtable_types.h > @@ -9,11 +9,13 @@ > #ifdef CONFIG_ARCH_HAS_HW_PTE_T > typedef struct __hw_pte_t { pte_t __pte; } hw_pte_t; > #define __pte_from_hw(pte) ((pte).__pte) > +#define __hw_pte(pte) ((hw_pte_t) { (pte) }) same comment as for patch 2; wouldn't this be better off in the generic series? Thanks, Ryan > > #define hw_pte_val(x) pte_val((x).__pte) > #else > #define hw_pte_t pte_t > #define __pte_from_hw(pte) (pte) > +#define __hw_pte(pte) (pte) > > #define hw_pte_val(x) pte_val(x) > #endif >