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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id w4sm19835679wmc.13.2021.02.01.00.46.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Feb 2021 00:46:38 -0800 (PST) To: Sean Christopherson Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, jmattson@google.com, stable@vger.kernel.org References: <20210129101912.1857809-1-pbonzini@redhat.com> From: Paolo Bonzini Subject: Re: [PATCH v2] KVM: x86: Allow guests to see MSR_IA32_TSX_CTRL even if tsx=off Message-ID: <37be5fb8-056f-8fba-3016-464634e069af@redhat.com> Date: Mon, 1 Feb 2021 09:46:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/01/21 17:58, Sean Christopherson wrote: > On Fri, Jan 29, 2021, Paolo Bonzini wrote: >> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c >> index 76bce832cade..15733013b266 100644 >> --- a/arch/x86/kvm/x86.c >> +++ b/arch/x86/kvm/x86.c >> @@ -1401,7 +1401,7 @@ static u64 kvm_get_arch_capabilities(void) >> * This lets the guest use VERW to clear CPU buffers. > > > This comment be updated to call out the new TSX_CTRL behavior. > > /* > * On TAA affected systems: > * - nothing to do if TSX is disabled on the host. > * - we emulate TSX_CTRL if present on the host. > * This lets the guest use VERW to clear CPU buffers. > */ Ok. >> */ >> if (!boot_cpu_has(X86_FEATURE_RTM)) >> - data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); >> + data &= ~ARCH_CAP_TAA_NO; > > Hmm, simply clearing TSX_CTRL will only preserve the host value. Since > ARCH_CAPABILITIES is unconditionally emulated by KVM, wouldn't it make sense to > unconditionally expose TSX_CTRL as well, as opposed to exposing it only if it's > supported in the host? I.e. allow migrating a TSX-disabled guest to a host > without TSX. Or am I misunderstanding how TSX_CTRL is checked/used? I'm a bit wary of having a combination (MDS_NO=0, TSX_CTRL=1) that does not exist on bare metal. There are other cases where such combinations can happen, especially with the Spectre and SSBD mitigations (for example due to AMD CPUID bits for Intel processors), but at least those are just redundancies in the CPUID bits and it's more likely that the guest does something sensible with them. Paolo >> else if (!boot_cpu_has_bug(X86_BUG_TAA)) >> data |= ARCH_CAP_TAA_NO; >> >> -- >> 2.26.2 >> >