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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id z21-20020a2e8e95000000b002a634bfa224sm2557662ljk.40.2023.04.18.05.18.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Apr 2023 05:18:31 -0700 (PDT) Message-ID: <38478a18-d60f-924f-f8cd-3ba44d0f1c65@linaro.org> Date: Tue, 18 Apr 2023 14:18:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v2 06/17] drm/msm/dpu: Remove extraneous register define indentation Content-Language: en-US To: Marijn Suijten , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Adam Skladowski , Loic Poulain , Bjorn Andersson , Kuogee Hsieh , Robert Foss , Vinod Koul , Rajesh Yadav , Jeykumar Sankaran , Neil Armstrong , Chandan Uddaraju Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , Archit Taneja , Sravanthi Kollukuduru References: <20230411-dpu-intf-te-v2-0-ef76c877eb97@somainline.org> <20230411-dpu-intf-te-v2-6-ef76c877eb97@somainline.org> From: Konrad Dybcio In-Reply-To: <20230411-dpu-intf-te-v2-6-ef76c877eb97@somainline.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17.04.2023 22:21, Marijn Suijten wrote: > A bunch of registers are indented with two extra spaces, looking as if > these are values corresponding to the previous register which is not the > case, rather these are simply also register offsets and should only have > a single space separating them and the #define keyword. > > Signed-off-by: Marijn Suijten > --- Reviewed-by: Konrad Dybcio Konrad > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 41 +++++++++++++++-------------- > 1 file changed, 21 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index b9dddf576c02..1d22d7dc99b8 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -38,26 +38,27 @@ > #define INTF_ACTIVE_DATA_HCTL 0x068 > #define INTF_FRAME_LINE_COUNT_EN 0x0A8 > #define INTF_FRAME_COUNT 0x0AC > -#define INTF_LINE_COUNT 0x0B0 > - > -#define INTF_DEFLICKER_CONFIG 0x0F0 > -#define INTF_DEFLICKER_STRNG_COEFF 0x0F4 > -#define INTF_DEFLICKER_WEAK_COEFF 0x0F8 > - > -#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 > -#define INTF_PANEL_FORMAT 0x090 > -#define INTF_TPG_ENABLE 0x100 > -#define INTF_TPG_MAIN_CONTROL 0x104 > -#define INTF_TPG_VIDEO_CONFIG 0x108 > -#define INTF_TPG_COMPONENT_LIMITS 0x10C > -#define INTF_TPG_RECTANGLE 0x110 > -#define INTF_TPG_INITIAL_VALUE 0x114 > -#define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 > -#define INTF_TPG_RGB_MAPPING 0x11C > -#define INTF_PROG_FETCH_START 0x170 > -#define INTF_PROG_ROT_START 0x174 > -#define INTF_MUX 0x25C > -#define INTF_STATUS 0x26C > +#define INTF_LINE_COUNT 0x0B0 > + > +#define INTF_DEFLICKER_CONFIG 0x0F0 > +#define INTF_DEFLICKER_STRNG_COEFF 0x0F4 > +#define INTF_DEFLICKER_WEAK_COEFF 0x0F8 > + > +#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 > +#define INTF_PANEL_FORMAT 0x090 > +#define INTF_TPG_ENABLE 0x100 > +#define INTF_TPG_MAIN_CONTROL 0x104 > +#define INTF_TPG_VIDEO_CONFIG 0x108 > +#define INTF_TPG_COMPONENT_LIMITS 0x10C > +#define INTF_TPG_RECTANGLE 0x110 > +#define INTF_TPG_INITIAL_VALUE 0x114 > +#define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 > +#define INTF_TPG_RGB_MAPPING 0x11C > +#define INTF_PROG_FETCH_START 0x170 > +#define INTF_PROG_ROT_START 0x174 > + > +#define INTF_MUX 0x25C > +#define INTF_STATUS 0x26C > > #define INTF_CFG_ACTIVE_H_EN BIT(29) > #define INTF_CFG_ACTIVE_V_EN BIT(30) >