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Thu, 09 May 2024 19:27:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 449JRCwQ022111 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 9 May 2024 19:27:12 GMT Received: from [10.110.104.129] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 9 May 2024 12:27:11 -0700 Message-ID: <389f63a0-c00f-719b-085f-d562c2b5da08@quicinc.com> Date: Thu, 9 May 2024 12:27:10 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH] drm/msm/dpu: fix encoder irq wait skip Content-Language: en-US To: =?UTF-8?B?QmFybmFiw6FzIEN6w6ltw6Fu?= , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: , , , References: <20240509-irq_wait-v1-1-41d653e3784e@gmail.com> From: Abhinav Kumar In-Reply-To: <20240509-irq_wait-v1-1-41d653e3784e@gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TIX1gsMOKwQammEIUK1RvTdPG5U7ZaA6 X-Proofpoint-ORIG-GUID: TIX1gsMOKwQammEIUK1RvTdPG5U7ZaA6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-09_11,2024-05-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 malwarescore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405090136 On 5/9/2024 10:39 AM, Barnabás Czémán wrote: > The irq_idx is unsigned so it cannot be lower than zero, better > to change the condition to check if it is equal with zero. > It could not cause any issue because a valid irq index starts from one. > > Signed-off-by: Barnabás Czémán > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > I think we also need Fixes: 5a9d50150c2c ("drm/msm/dpu: shift IRQ indices by 1") With that, Reviewed-by: Abhinav Kumar > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 119f3ea50a7c..cf7d769ab3b9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -428,7 +428,7 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, > return -EWOULDBLOCK; > } > > - if (irq_idx < 0) { > + if (irq_idx == 0) { > DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n", > DRMID(phys_enc->parent), func); > return 0; > > --- > base-commit: 704ba27ac55579704ba1289392448b0c66b56258 > change-id: 20240509-irq_wait-49444cea77e2 > > Best regards,