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([2a0a:ef40:e16:1f01:b442:1e4f:d5a4:2a21]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49c60d9fff8sm345018f8f.52.2026.11.12.09.24.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Nov 2026 09:24:42 -0800 (PST) Message-ID: <38a09248-032a-4144-9e56-6d52eef8c077@linaro.org> Date: Thu, 12 Nov 2026 17:24:41 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] clk: ti: fapll: Fix clock speed calculation To: Brian Masney , Ettore Chimenti Cc: Tero Kristo , Stephen Boyd , Brian Masney , Jerome Brunet , Tony Lindgren , Michael Turquette , Rouven Czerwinski , linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261028-patch-ektor5-dm8168-clk-v2-0-dc6bf0fabae4@linaro.org> <20261028-patch-ektor5-dm8168-clk-v2-2-dc6bf0fabae4@linaro.org> <179444595968.1126566.8596406047613157255.b4-review@b4> Content-Language: en-GB From: Andrew Goodbody In-Reply-To: <179444595968.1126566.8596406047613157255.b4-review@b4> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/11/2026 01:12, Brian Masney wrote: > Hi Ettore, > >> The fractional part of the divider was being treated as 1/10000000 >> whereas it is in fact 1/2^24 (1/16777216). This led to incorrect clock >> speeds being reported when a fractional divider was in use. Correct it. >> As well as fixing the clock speed calculation when read, also update the >> calculation on set in a similar manner. >> >> Fixes: 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x") >> Signed-off-by: Andrew Goodbody > > Should there be a Co-Developed-By here and on the other patches? Not sure about that. This is my patch but is being submitted by Ettore in a series of patches that affect the clk system. We were working together on a project and at times each produced patches. Ettore has collected together this series for submission. >> Signed-off-by: Ettore Chimenti >> --- >> drivers/clk/ti/fapll.c | 10 +++++----- >> 1 file changed, 5 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c >> index ae2f6fed10f6..8ab9acd57b60 100644 >> --- a/drivers/clk/ti/fapll.c >> +++ b/drivers/clk/ti/fapll.c >> @@ -336,8 +336,8 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, >> v = readl_relaxed(synth->freq); >> synth_int_div = (v >> 24) & 0xf; >> synth_frac_div = v & 0xffffff; >> - synth_div_freq = (synth_int_div * 10000000) + synth_frac_div; >> - rate *= 10000000; >> + synth_div_freq = (synth_int_div * 16777216) + synth_frac_div; >> + rate *= 16777216; > > The 16777216 magic number appears multiple times. Plugging this into my > calculator, I see it's 1 << 24. How about adding some defines: > > #define SYNTH_FRAC_DIV_BITS 24 > #define SYNTH_FRAC_DIV_SCALE BIT(SYNTH_FRAC_DIV_BITS) Sure, can do. Andrew > Brian >