From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B034C34DB7C; Mon, 12 Jan 2026 13:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768223123; cv=none; b=NMIEjM+icCiMMSshzCUCK4Uto8LsCudAj4Nug3FTG4Ti0sPsG9u6GdH+tXJ0hw+nJLWgKjzf9tvbAX4Cm4/Yqic1v0kFZTiMXIoMTuDjaYpviUn+UnJNiVg7+KxMSE9So7cyQHE7uFk3zppPHl/WXrEeCQqSWKna79qOEwJx6R0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768223123; c=relaxed/simple; bh=flvvAsmXXQZQ8BR4vFmMtqKqClj4vBglabEbpV7HO+I=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=iYh6c+rEEjw/srHo2kpznbpEkVS4hjPEYRJmdIMjWe03yP7E+NFyj0SgPsQvyYFE9LOs5O03l+QzPAYV6hWsRl75dD9rPwX04+iTlDtNg6eVdDgjrJhZIL/cJlZXrJeZXc08Tf886lR6Puy1PA1XTtNxt/cpgfaaXhdCaxjiSAc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=FNb9xu+t; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="FNb9xu+t" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=IaMUeZ61KcIsfoWqo/Ut8gaTEoMImMfZQvRUuQXMr0A=; b=FNb9xu+tpIA986WGcfc5GGMrjd n3ULGTmqRy2V3mm8zr2D6gvBUA2NkIUJ5RPDBO5YDNYtVN/nexDz17BCrQr++Rw1YextI9pzoPX5k P8ldWbbwbEiYZhxv1cmOtiIiMuBQki4Ye/NY65H1s5cPa9L0S0FmKm0Q+vvaX+9Tw16Q=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1vfHba-002TRY-Cd; Mon, 12 Jan 2026 14:05:10 +0100 Date: Mon, 12 Jan 2026 14:05:10 +0100 From: Andrew Lunn To: Siddharth Vadapalli Cc: vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, sjakhade@cadence.com, rogerq@kernel.org, thomas.richard@bootlin.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srk@ti.com Subject: Re: [PATCH v3 2/2] phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk Message-ID: <38da25fd-a402-4b34-8131-0655bccc1953@lunn.ch> References: <20260112054636.108027-1-s-vadapalli@ti.com> <20260112054636.108027-3-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260112054636.108027-3-s-vadapalli@ti.com> On Mon, Jan 12, 2026 at 11:16:31AM +0530, Siddharth Vadapalli wrote: > From: Swapnil Jakhade > > Add register sequences for PCIe + XAUI multilink configuration for > 100MHz reference clock. > > The register sequences are fetched from a table by indexing entries based > on unique 'keys' generated by the Bitwise OR defined below: > REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE > > As of now, LINK_TYPE is a 3-bit value corresponding to the PHY type. > With the introduction of TYPE_XAUI, we need a 4-bit value to represent > the LINK_TYPE as TYPE_XAUI has the numerical value 8. Hence, extend the > LINKx_MASK macros to 4-bit masks. While at it, extend REFCLKx_MASK macros > as well to 4-bit masks to support reference clock frequencies that will be > added in the future. > > Adjust the 'LINKx_SHIFT' and the 'REFCLKx_SHIFT' macros to account for > the aforementioned changes made to the masks. > > Signed-off-by: Swapnil Jakhade > [s-vadapalli: elaborated on changes made to macros in the commit message] > Signed-off-by: Siddharth Vadapalli Reviewed-by: Andrew Lunn Andrew