From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7121C331EBF for ; Thu, 11 Jun 2026 12:34:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781181271; cv=none; b=IGbSnNXR4nNYWopQ7cSJ4lED9AYYzPslJU1kRtZD7fzyPXi0P3BgqlShGnv7DE7keg4bVxtO6iDfWM2NyqzwoG02x/0Bvp3aSns1UIxQHsj/SIsuDFjFSeMY8yjBQJaPvFZnoMANLzRTrBVqftCPBiTwPlN4sp0RxNhWr4SHGjc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781181271; c=relaxed/simple; bh=GM32saeASmaz4if372xZH1/viClkocEGw0aQEB81ZZ8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=N9S4o3LIRbbWWOWo2g+FDfEz/ck6ryBQBOA1EBcF8SlWZbgpNHQc+N/EL13SQaRm9mkTHfvD7331FnUHcQeIE8l6p0VaQ+muZh7VldSufaB3VQONzGNSiywSDOgWj3c4IdkEuRVsUrPVcMqGZ5lhx2pAdEmGSbcDud/FFccEN4k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=UO8fXxIR; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="UO8fXxIR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1781181268; bh=GM32saeASmaz4if372xZH1/viClkocEGw0aQEB81ZZ8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=UO8fXxIRvl8X+2IN3ioGsA87bY3fVCCXwCcJjo+thI/jKDT2IcJ5v79i4tnfwq42O 3QgjWsYrBG9e4MdpF1Wbir4JI4qrJSVfK+GZPDbPD+SfEQaNys9uJxbfGiz0gDB4fc gt9sA0DcLt4YRibXe4H4ZlA6toZDq7FXBM1ikmhNbYddIUcdw3K8jypOFjCzC5PIdh sFrJlTlAiUroICwy9Rhy8JSwf68ZMh5xMYdJAts1blQ1l88FURSxP/s/kTzzouIiGJ wnhSPLvFiH+YxbUltYjAnKzFPszfdMO6IHIy5mm9eBzRBLvE8yoO3VSNdWnUYO1E6k dYhBamWo0jPNw== Received: from [100.64.0.241] (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 46C0017E0191; Thu, 11 Jun 2026 14:34:28 +0200 (CEST) Message-ID: <38f0e334-bf28-4c8d-aa3c-e075c31a0c1e@collabora.com> Date: Thu, 11 Jun 2026 15:34:27 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups To: Vinod Koul Cc: Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?Q?Thomas_Niederpr=C3=BCm?= , Simon Wright References: <20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com> Content-Language: en-US From: Cristian Ciocaltea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/11/26 2:26 PM, Vinod Koul wrote: > On 03-06-26, 13:27, Cristian Ciocaltea wrote: >> On 5/20/26 10:05 PM, Cristian Ciocaltea wrote: >>> Hi Vinod, >>> >>> On 5/11/26 9:21 PM, Cristian Ciocaltea wrote: >>>> This series provides a set of bug fixes and cleanups for the Rockchip >>>> Samsung HDPTX PHY driver. >>>> >>>> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate >>>> calculation and synchronization issues. Specifically, it fixes edge >>>> cases where the PHY PLL is pre-programmed by an external component (like >>>> a bootloader) or when changing the color depth (bpc) while keeping the >>>> modeline constant. Because the Common Clock Framework .set_rate() >>>> callback might not be invoked if the pixel clock remains unchanged, this >>>> previously led to out-of-sync states between CCF and the actual HDMI PHY >>>> configuration. >>>> >>>> The second part focuses on code cleanups and modernizing the register >>>> access. Now that dw_hdmi_qp driver has fully switched to using >>>> phy_configure(), we can drop the deprecated TMDS rate setup workarounds >>>> and the restrict_rate_change flag logic. Finally, it refactors the >>>> driver to consistently use standard bitfield macros. >>>> >>>> Signed-off-by: Cristian Ciocaltea >>>> --- >>>> Changes in v2: >>>> - Collected Tested-by tags from Thomas and Simon >>>> - Fixed a typo in commit description of patch 1 >>>> - Added a comment in patch 2 explaining why PLL config errors are >>>> ignored for rk_hdptx_phy_consumer_get() >>>> - Added a missed FIELD_GET conversion for lcpll_hw.pms_sdiv in patch 6 >>>> - Rebased onto latest phy/fixes >>>> - Link to v1: https://lore.kernel.org/r/20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com >>> >>> In case you missed my comments from last week on the Sashiko AI review findings >>> - in short, I don't think there is anything to worry about and the series should >>> be fine to apply as-is. Please let me know if you would still prefer a new >>> revision. >> Kind reminder.. > > Please post a new revision based on phy/next Done (also addressed the confirmed Sashiko reported issues): https://lore.kernel.org/all/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com/ Thanks, Cristian