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Tue, 06 Jan 2026 23:22:19 -0800 (PST) Message-ID: <39019203631fdd183fb5ddaa7fada5da5f2a31ad.camel@linaro.org> Subject: Re: [PATCH v7 3/4] clk: samsung: Implement automatic clock gating mode for CMUs From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Peter Griffin , Krzysztof Kozlowski , Alim Akhtar , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com, Rob Herring , Conor Dooley Date: Wed, 07 Jan 2026 07:22:44 +0000 In-Reply-To: <20251222-automatic-clocks-v7-3-fec86fa89874@linaro.org> References: <20251222-automatic-clocks-v7-0-fec86fa89874@linaro.org> <20251222-automatic-clocks-v7-3-fec86fa89874@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-2+build3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi, On Mon, 2025-12-22 at 10:22 +0000, Peter Griffin wrote: > Update exynos_arm64_init_clocks() so that it enables the automatic clock > mode bits in the CMU option register if the auto_clock_gate flag and > option_offset fields are set for the CMU. To ensure compatibility with > older DTs (that specified an incorrect CMU reg size), detect this and > fallback to manual clock gate mode as the auto clock mode feature depends > on registers in this area. >=20 > The CMU option register bits are global and effect every clock component = in > the CMU, as such clearing the GATE_ENABLE_HWACG bit and setting GATE_MANU= AL > bit on every gate register is only required if auto_clock_gate is false. >=20 > Additionally if auto_clock_gate is enabled the dynamic root clock gating > and memclk registers will be configured in the corresponding CMUs sysreg > bank. These registers are exposed via syscon, so the register > samsung_clk_save/restore paths are updated to also take a regmap. The implementation described in this paragraph this causes pm-runtime to stop working for the CMU if auto clock gating is enabled. See below. > [...] > diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c > index c149ca6c221725195faeb76b0d73374c3b48261b..06ea5deef4ee2ffb87dcd1410= 2561886ea80b7bc 100644 > --- a/drivers/clk/samsung/clk.c > +++ b/drivers/clk/samsung/clk.c > [...] > @@ -357,6 +489,37 @@ void __init samsung_cmu_register_clocks(struct samsu= ng_clk_provider *ctx, > =C2=A0 samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks); > =C2=A0} > =C2=A0 > +/* Each bit enable/disables DRCG of a bus component */ > +#define DRCG_EN_MSK GENMASK(31, 0) > +#define MEMCLK_EN BIT(0) > + > +/* Enable Dynamic Root Clock Gating (DRCG) of bus components */ > +void samsung_en_dyn_root_clk_gating(struct device_node *np, > + =C2=A0=C2=A0=C2=A0 struct samsung_clk_provider *ctx, > + =C2=A0=C2=A0=C2=A0 const struct samsung_cmu_info *cmu) > +{ > + if (!ctx->auto_clock_gate) > + return; > + > + ctx->sysreg =3D syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); With this, the CMU driver (e.g. cmu_hsi0) now gets a reference to the respe= ctive sysreg (sysreg_hsi0), which in turn creates a regmap with a clock handle (CLK_GOUT_HSI0_SYSREG_HSI0_PCLK), and the clock is 'prepared'. Hence the CM= U providing this clock (cmu_hsi0) is not idle anymore, and runtime PM for thi= s CMU can't kick in anymore I see two straight forward options to fix this: 1) The easiest fix is to just drop the clock from the sysreg DT node. The s= ysreg clock shouldn't matter now, as the whole CMU is in auto mode now anyway. 2) change above code to use device_node_to_regmap() which ignores resources= (the sysreg clock in the example case), and manage the clock manually during sav= e and restore in samsung_clk_save() and samsung_clk_restore() Any better ideas? Cheers, Andre'