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From: "Johnny-CC Chang (張晋嘉)" <Johnny-CC.Chang@mediatek.com>
To: "lukas@wunner.de" <lukas@wunner.de>
Cc: Project_Global_Digits_Upstream_Group
	<Project_Global_Digits_Upstream_Group@mediatek.com>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>
Subject: Re: [PATCH] PCI: Mark Nvidia GB10 to avoid bus reset
Date: Tue, 18 Nov 2025 09:39:18 +0000	[thread overview]
Message-ID: <39028d84844a08b8b716eb3941cc02562d21dc84.camel@mediatek.com> (raw)
In-Reply-To: <aRWnYCI6Ax14XNJq@wunner.de>

On Thu, 2025-11-13 at 10:39 +0100, Lukas Wunner wrote:
> On Thu, Nov 13, 2025 at 04:44:06PM +0800, Johnny Chang wrote:
> > Nvidia GB10 PCIe hosts will encounter problem occasionally
> > after SBR(secondary bus reset) is applied.
> 
> Could you elaborate what kinds of problems occur, how often they
> occur, etc?

There is about 1/1000 chance that after SBR is applied, any further
access via this root port will be blocked and make system crash. 

Thanks,

Johnny

  reply	other threads:[~2025-11-18  9:39 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-13  8:44 Johnny Chang
2025-11-13  9:39 ` Lukas Wunner
2025-11-18  9:39   ` Johnny-CC Chang (張晋嘉) [this message]
2026-01-14  6:39     ` Johnny-CC Chang (張晋嘉)
2026-01-14 17:28       ` Bjorn Helgaas
2026-01-15 20:11         ` Terje Bergstrom
2026-01-15 20:53           ` Bjorn Helgaas
2026-01-15 21:55             ` Terje Bergstrom
2026-01-15 22:11 ` Bjorn Helgaas

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