From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from canpmsgout01.his.huawei.com (canpmsgout01.his.huawei.com [113.46.200.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 421EB1F5842; Thu, 5 Feb 2026 01:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.216 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770254298; cv=none; b=XzfE6GTi/LV9Pp6GxWSVTggvO984TYWJ4Vf2+P4pNzUZrnhuuVpzOKyeVmMgjarVsc2v5SGpPn+WXJARGzJXngXPpPnoRXDAJRCanb0FBKq4FUrO4fy1avYnt0cUXTEYYl7rcsj53E0V18cQYFdeVdEFuDEmvKWSIM2BDggv03k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770254298; c=relaxed/simple; bh=myCYmedByJpoEdUbCWYLEQPymvHMA0rNtV1X53P8u/U=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=N4DAW9uS3OQaA4qDfesu6qTRfaQKAuEXwAtHG3A8JX5yEc8y4wbgSWiQcRgZvwqnUTW5mbMeiXKgtC9gAuqLvICy4jXldJGAe+tndBbTnYjCTJomOe62yT4182gCQkTEM4HnITCNXWiDKKOLjUKsr354YiygTGWnGX2pwrimkOA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=UilPor7K; arc=none smtp.client-ip=113.46.200.216 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="UilPor7K" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=xI/2KWmPVAxqEykMkOoqWIvnmzgEQ82nJSITMhdtX+M=; b=UilPor7KF1mQGZU80iF1wm9uhANb7eLpdUAAfT1EbAVqyz5f3MuJC2tHNZlVA+SgG/hUuthBb RxsdNeqfsHmppNRpkAktCBK4yL8IkwzfAa3s1QbgOejRAyaXY1R+f43osfcPzm2Pb9yzWIkUTqk OCgU5AQ7rP5i+K5xwCtHvW4= Received: from mail.maildlp.com (unknown [172.19.162.144]) by canpmsgout01.his.huawei.com (SkyGuard) with ESMTPS id 4f5zkb65ZLz1T4GK; Thu, 5 Feb 2026 09:13:43 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 2F21540567; Thu, 5 Feb 2026 09:18:07 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 5 Feb 2026 09:18:05 +0800 Message-ID: <39165a75-bf07-7e3c-6ed5-9431958b706a@huawei.com> Date: Thu, 5 Feb 2026 09:18:04 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH v12 00/13] arm64: entry: Convert to Generic Entry To: Thomas Gleixner , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20260203133728.848283-1-ruanjinjie@huawei.com> <87bji552uk.ffs@tglx> <2699bcdc-8d56-7fe9-fa9a-a3d61476e806@huawei.com> <87y0l823o9.ffs@tglx> Content-Language: en-US From: Jinjie Ruan In-Reply-To: <87y0l823o9.ffs@tglx> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To dggpemf500011.china.huawei.com (7.185.36.131) On 2026/2/4 18:39, Thomas Gleixner wrote: > On Wed, Feb 04 2026 at 09:28, Jinjie Ruan wrote: >> On 2026/2/3 22:16, Thomas Gleixner wrote: >>> On Tue, Feb 03 2026 at 21:37, Jinjie Ruan wrote: >>>> Currently, x86, Riscv, Loongarch use the Generic Entry which makes >>>> maintainers' work easier and codes more elegant. arm64 has already >>>> successfully switched to the Generic IRQ Entry in commit >>>> b3cf07851b6c ("arm64: entry: Switch to generic IRQ entry"), it is >>>> time to completely convert arm64 to Generic Entry. >>>> >>>> The goal is to bring arm64 in line with other architectures that already >>>> use the generic entry infrastructure, reducing duplicated code and >>>> making it easier to share future changes in entry/exit paths, such as >>>> "Syscall User Dispatch". >>>> >>>> This patch set is rebased on "sched/core". And the performance >>> >>> Why are you using sched/core, which contains a lot of unrelated >>> changes. core/entry is the one which has the prerequisites and nothing >>> else.... >> >> By the way，it looks like core/entry and arm64 for-next/entry have >> diverged: the first three patches of this series are already in arm64 >> for-next/entry but missing from core/entry. >> Perhaps the two branches should be reconciled so that both contain the >> same baseline. > > The first three patches of this series are ARM specific and have nothing > to do with the queued core/entry changes in tip. They are independent of > each other and these three ARM64 changes have no business in my tree. > > If the ARM64 folks want to apply the rest of your series then they have > to pull the core/entry branch into their for-next/core branch first so > the whole thing builds. > > But given that the merge window opens on sunday, this is probably moot > anyway and the rest of this series can go on top of rc1 in the ARM64 > tree w/o any further complications. Thanks for the clear explanation, many thanks as well for the extensive review work and the prompt replies on the generic entry changes. Regards, Jinjie > > Thanks, > > tglx >