From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE0C74D597F; Mon, 19 Oct 2026 10:01:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792404072; cv=none; b=pGxXWbsko+zsxeQchpF9ZFjs4xL5SrgA1SAYOTTKZto3UneistRGA1qZeghoZYjAu8dGf6tErwpVzUzVH+JZyF3JxOsHJzPnexiTNAGwha4L2Wt3j8Wd2EQL+4ica0CvVGT2E9FXZwhcljAq2g/nERMr2AlfGSTVET+2bRoX4eQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792404072; c=relaxed/simple; bh=EKWfrIRBQN/A0hWazzILMvN+1tgZIZ4mudS5/pWSEPY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=aQhSbxhuXi2Am7BovJpxoj1i0jMh7SfmXY/orXYaKpt2e2ZuEQwRbTf7t6wAsi/OrgdDfLVoHARkLxGlnhEaWdFKyH+ICzMwtwfFBt/4QXzBKCj7gNDZygIsVJCcsZOtQ9THDO/0gEAAmSEAT7nQwdY3MADXffdofR7sUpdEQoU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YOOlmR99; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YOOlmR99" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97A1C1F000C4; Mon, 19 Oct 2026 10:01:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792404070; bh=6HDV2HcLkfwQjSgKzpnVgoK+4ivvoEHdz75ohcQoHhk=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=YOOlmR992iCkxzo8lLqrfm6QBsTap8iuF1rxQ7iZ7zCq94SxSviXJ4s0jj5xMgN1y u3ecZrigLfaBBcyhIz5vjV60zaZ8SofK/7xpiH/LxFUDiFMl70Z6IAyeGo93P8Mj57 VtUvig875jusO7GHu1mfiqf/vuzWfdqtG9MKdA9KZGR3YNJ7/8mmKDF8NzsV0/VSvl XZFWML62NHsQJGTCNgmCw50qX7m6CKAfRJm7AibA0nhiEyYGiANTE6Uj0/HYm0EMrs ZhQkKsBMkT1XLi6zAjSXSrNOJv2P2x5IYi0De3vs4hhiZcW+YxkElKcvRSg4jkTtOw E6yHw9RxSV/Rw== Message-ID: <392642ad-3bac-48bc-9199-8c3923c588c2@kernel.org> Date: Mon, 19 Oct 2026 11:01:05 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/7] phy: qcom-mipi-csi2: Add sa8775p D-PHY support To: Anusha Arun Nandi , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, mani@kernel.org Cc: gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, loic.poulain@oss.qualcomm.com, vladimir.zapolskiy@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261016235502.2274268-1-anusha.nandi@oss.qualcomm.com> <20261016235502.2274268-5-anusha.nandi@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-GB Autocrypt: addr=bod@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/10/2026 00:54, Anusha Arun Nandi wrote: > The timer-clock lookup in phy_qcom_mipi_csi2_probe() and the OPP > clkname passed to devm_pm_opp_set_clkname() were both hardcoded > string literals sized to x1e80100 ("timer"/"core"). Add > timer_clk_name/opp_clk_name to struct mipi_csi2phy_soc_cfg so each > SoC can declare its own clock-name strings; x1e80100's soc_cfg now > declares "timer"/"core" explicitly, with no behaviour change. > SA8775P reuses the same "timer"/"core" names as x1e80100 for this > pair of clocks. LoL I had that in the last design and review said "hard code it" happy to agree with myself in the past, however this change should be standalone and precede the Lemans work. > SA8775P's CSIPHY has a single power-domain, the Titan Top GDSC, > matching the legacy in-tree CAMSS driver's sa8775p_resources.pd_name > = "top" and the existing lemans.dtsi camss node. Like x1e80100's own > "top" domain, it is not OPP-scaled, only kept enabled. > > Signed-off-by: Anusha Arun Nandi > --- > .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 112 ++++++++++++++++++ > .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 5 +- > drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 4 + > 3 files changed, 119 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > index 966d79c98f9b..85e89235f7c9 100644 > --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > @@ -380,6 +380,118 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { > .num_supplies = ARRAY_SIZE(x1e_supplies), > .clk_names = (const char **)x1e_clks, > .num_clk = ARRAY_SIZE(x1e_clks), > + .timer_clk_name = "timer", > + .opp_clk_name = "core", > .genpds = x1e_genpds, > .num_genpds = ARRAY_SIZE(x1e_genpds), > }; Yes but split it up - "remove hard coded timer and opp names" - actually you want to make the OPP optional no ? In which case you'd expect to see a patch to make OPPs optional - instead of folding that into a functionality drop. Because say we want to revert or re-order the addition of Lemans in the git log - we then have the problem of mixed functionality. Or say I want to cherry-pick a backport - I don't necessarily want to include lots of SoC specific stuff that doesn't affect my part. => More granular patches. --- bod