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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7ra4Zxn+tIUCIf4AbKmNIsYfBBvxPu7h0pCf8rZ4yPJpPk2QXCB2WjHLasdnKUHgl1sKoUAz0YbPOzknEElclTcQMAbJgzRbPSvxoD4EivKPQ1aneDtkH/qjQ7gSROCPNvg32ej9gdCRSLrbNmORJwTkGYoxgNICyJL4eIBkls3r3/QuSJG4JaNB8vU9yk3VZ0Vn5iT2CsnOQ6uvTVfAetNDdgCwp+lytqsZsXJNuqVX+kLlQB4O+bn+/3MzbDVP4MBoW3b/2+tpCm50usU+CL4GTYAKH9Jo/Lp/DwkoXBuYsawhEDLlXg5fckKduG2MCAb16qKqGjHbsJzVMykE5cbp8hrU5vjvE5/m0dhsBnLxhtjKMyZl4azrOEpF26kWLV9J9X6a+eu47iXBU0NtEYugMHvpMT17FwvcNbDVmb6VqMj/wWhVbcbAzMfkfrJO X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2026 21:47:30.5630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d11d2623-152b-43da-6f66-08de62a4aa6c X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR10MB7649 On 2/2/26 11:02, Péter Ujfalusi wrote: > > > On 30/01/2026 07:10, Sen Wang wrote: >> McASP has dedicated clock & frame sync registers for both transmit >> and receive. Currently McASP driver only supports synchronous behavior and >> couples both TX & RX settings. >> >> Add logic that enables asynchronous mode via ti,async-mode property. In >> async mode, playback & record can be done simultaneously with different >> audio configurations (tdm slots, tdm width, audio bit depth). >> >> Note the ability to have different tx/rx DSP formats (i2s, dsp_a, etc.), >> while possible in hardware, remains to be a gap as it require changes >> to the corresponding machine driver interface. >> >> Existing IIS (sync mode) and DIT mode logic remains mostly unchanged. >> Exceptions are IIS mode logic that previously assumed sync mode, which has >> now been made aware of the distinction. And shared logic across all modes >> also now checks for McASP tx/rx-specific driver attributes. Those >> attributes have been populated according to the original extent, ensuring >> no divergence in functionality. >> >> Constraints no longer applicable for async mode are skipped. >> Clock selection options have also been added to include rx/tx-only clk_ids, >> exposing independent configuration via the machine driver as well. >> >> Note that asynchronous mode is not applicable for McASP in DIT mode, >> which is a transmitter-only mode to interface w/ self-clocking formats. >> >> Signed-off-by: Sen Wang >> --- >> include/linux/platform_data/davinci_asp.h | 3 +- >> sound/soc/ti/davinci-mcasp.c | 487 +++++++++++++++++----- >> sound/soc/ti/davinci-mcasp.h | 10 + >> 3 files changed, 398 insertions(+), 102 deletions(-) >> >> diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c >> > > static void mcasp_start_rx(struct davinci_mcasp *mcasp) >> { >> if (mcasp->rxnumevt) { /* enable FIFO */ >> @@ -230,13 +288,17 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp) >> /* >> * When ASYNC == 0 the transmit and receive sections operate >> * synchronously from the transmit clock and frame sync. We need to make >> - * sure that the TX signlas are enabled when starting reception. >> + * sure that the TX signals are enabled when starting reception. >> + * Else set pin to be output when McASP is the master > > In new code - while it might not match with old code - use producer > instead of master. > > Otherwise it looks nice, I trust you have tested the sync and DIT mode. > > With this nitpick addressed: > Acked-by: Peter Ujfalusi > Hi Péter, thanks for your review I'll use inclusive terminology (producer) instead. I've functionally tested IIS sync mode. For DIT mode, since I don't have hardware available, I've only done a register dump in comparison, during idle, playback & shutdown - all registers in effect stay unchanged. Will post a V2 shortly with all the corrections. Best, Sen Wang