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Tue, 28 Apr 2026 10:21:35 -0700 (PDT) X-Received: by 2002:a17:903:1a86:b0:2b2:3eec:c75b with SMTP id d9443c01a7336-2b97bfc3323mr31903665ad.2.1777396895084; Tue, 28 Apr 2026 10:21:35 -0700 (PDT) Received: from [192.168.1.4] ([122.177.243.58]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b97ac7858csm34088535ad.49.2026.04.28.10.21.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Apr 2026 10:21:34 -0700 (PDT) Message-ID: <3938070f-5be7-466c-8967-6dc32b5ef372@oss.qualcomm.com> Date: Tue, 28 Apr 2026 22:51:25 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jagadeesh Kona Subject: Re: [PATCH 02/13] dt-bindings: clock: qcom,sm8550-dispcc: Add display CESTA support on SM8750 To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Neil Armstrong , Lee Jones , Ajit Pandey , Imran Shaik , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Maulik Shah , Taniya Das References: <20260420-cesta-sm870-dispcc-v1-0-eb27d845df9c@oss.qualcomm.com> <20260420-cesta-sm870-dispcc-v1-2-eb27d845df9c@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=abJRWxot c=1 sm=1 tr=0 ts=69f0eca0 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=EwI1ikYXukqkrg4G3Narhw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=uCKRraC37LqDOxPyBRsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: KzbOSRUdq5AYsOaJlFj6S8jKXUiv570O X-Proofpoint-ORIG-GUID: KzbOSRUdq5AYsOaJlFj6S8jKXUiv570O X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI4MDE2NyBTYWx0ZWRfX9sIPSxnottqP wZjJYpFZeSy6lqjOwHxsZ4uF59Ul8knt745kRWx1Cte3bm9FsVTYgFMuEESrB4kGJ2aWsA2115v ZZqo0DqguGlK6tBEi7yt8B49owVarUGJHh8BFqAE8Wr8N2wbDxOHmwsxd5gX8rs5xBaIjb/IYxY F2AdSGgS1xZdWPHAmClYh/7NBLqGPrjf0CuBoilwDsTsFBSld00cxbbHr+1cIcdUA32DH2N2Nu7 M/IiZVCVH89MrJ2/SEfXNjx+Mwo25UEcBkzdT62xoT79BgxVtzdVuSvEuHa1XTCUA4b0u16Wgni gW1EQ/yv1c69Dvr7/YXn49KN+WlUZjbCuYxam9kdx0vkTXawjZv0oNlST7RbI93/WNee5jtIppk hpsa6SC1LNpoJBlvSdLLEeL8S1Ddwzb6nS2ZgsiV6W9KCX3fT+vEpjMo52K+7nU/Sp3Y4i2yJbm dS+HdbMNSBxud/IrG4Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280167 On 4/20/2026 11:15 PM, Dmitry Baryshkov wrote: > On Mon, Apr 20, 2026 at 09:58:55PM +0530, Jagadeesh Kona wrote: >> On SM8750, a subset of DISPCC clocks is controlled by the display CESTA >> (Client State Aggregator) hardware. These clocks can be scaled to the >> desired frequency by sending votes to the display CRM(CESTA Resource >> manager) instead of programming DISPCC registers directly. >> >> Add bindings to allow the DISPCC node to reference the display CRM node >> for sending votes to CESTA hardware and the CRMC syscon regmap node >> which is used to read the frequency look up tables provided by CRM and >> populate this data in RCG's frequency tables for CESTA controlled clocks. >> >> Signed-off-by: Jagadeesh Kona >> --- >> .../bindings/clock/qcom,sm8550-dispcc.yaml | 48 ++++++++++++++++++++++ >> 1 file changed, 48 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml >> index 591ce91b8d54dd6f78a66d029882bcd94b53beda..3e049b2160a1781c866bb30b29f0da5c9e156b61 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml >> @@ -60,6 +60,18 @@ properties: >> A phandle to an OPP node describing required MMCX performance point. >> maxItems: 1 >> >> + qcom,crm: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + Phandle to the display CRM (CESTA Resource Manager) node, used to communicate >> + with the display CESTA (Client State Aggregator) hardware. > > Is it going to be shared by several entities? If not, can be make a part > of the dispcc and get rid of the extra CC <-> CRM API? > Thanks Dmitry for your review. Yes, clock is one of the consumer of CRM, but CRM can be used by interconnect drivers also for BW voting via CESTA. >> + >> + qcom,crmc-regmap: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + Phandle to the syscon providing the CRMC (CRM clock) regmap used >> + to read frequency LUTs (lookup tables) populated by the CRM. > > Why is this coming as a syscon? Why isn't it just a register region of > the dispcc? > The CRMC block is not part of the DISPCC register region; it is a separate sub‑block within the CRM(CESTA) address space. It contains clocks frequency lookup tables that the clock driver reads to populate RCG frequency tables. Since CRMC block is outside of DISPCC region and DISPCC driver doesn't own or manage the CRMC block and uses it just to read CRM controlled RCG's frequency tables, marked it as a syscon device. Thanks, Jagadeesh