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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-615a8f2c265sm19700788a12.26.2025.08.12.02.27.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 02:27:19 -0700 (PDT) Message-ID: <3939605c-7335-4401-ba32-b88ee900f1d5@oss.qualcomm.com> Date: Tue, 12 Aug 2025 11:27:16 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 02/11] PCI/bwctrl: Add support to scale bandwidth before & after link re-training To: Krishna Chaitanya Chundru , Bjorn Helgaas Cc: Bjorn Helgaas , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Jingoo Han , Lorenzo Pieralisi , Rob Herring , Jeff Johnson , Bartosz Golaszewski , Manivannan Sadhasivam , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, Jeff Johnson References: <20250711213602.GA2307197@bhelgaas> <55fc3ae6-ba04-4739-9b89-0356c3e0930c@oss.qualcomm.com> <68a78904-e2c7-4d4d-853d-d9cd6413760e@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <68a78904-e2c7-4d4d-853d-d9cd6413760e@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: mpe9j6pTyUORuNXVx84GeLWJnTGBk4Lb X-Proofpoint-ORIG-GUID: mpe9j6pTyUORuNXVx84GeLWJnTGBk4Lb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA2OCBTYWx0ZWRfXywUbJWsEs8sP TVWQb2GcwF54ASvr2xfloDloxwokMJ8OzIroknKxv5atR0etlufey/CBa2obhk1fxdXDYIaYw64 CWk3LslxqzWdeA1ciA+Up9R179ds88tvE8ss2DZHtT9pFDQLWSZYVOuRXtKLQv7BPZLhe+NZndW +aSf74gAjucRoTz8tmV1IWSCYmiW4LSY5IQnctJpQC4shai4BTql1sB41Mwhn4Qq7aVPctaGUsi NlFUu9nXLV9IoCulRnsU3AgGWuDeG2gHoLhhTzsWfSguyh+eIBy3fKXQpDmkA/N7ysbeTUCRAic EuCv2MSpKJCccKJLx7ChKweULqrUr88hxt+Fcc398bdd1SQgxItWs+npDAxfuL8BGmfMMGJGa8+ 5z7E3ogV X-Authority-Analysis: v=2.4 cv=YMafyQGx c=1 sm=1 tr=0 ts=689b08f9 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=PSSt48hOBszhu4C4aVgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_04,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110068 On 8/12/25 6:05 AM, Krishna Chaitanya Chundru wrote: > > > On 7/22/2025 4:33 PM, Krishna Chaitanya Chundru wrote: >> >> >> On 7/12/2025 4:36 AM, Krishna Chaitanya Chundru wrote: >>> >>> >>> On 7/12/2025 3:06 AM, Bjorn Helgaas wrote: >>>> On Mon, Jun 09, 2025 at 04:21:23PM +0530, Krishna Chaitanya Chundru wrote: >>>>> If the driver wants to move to higher data rate/speed than the current data >>>>> rate then the controller driver may need to change certain votes so that >>>>> link may come up at requested data rate/speed like QCOM PCIe controllers >>>>> need to change their RPMh (Resource Power Manager-hardened) state. Once >>>>> link retraining is done controller drivers needs to adjust their votes >>>>> based on the final data rate. >>>>> >>>>> Some controllers also may need to update their bandwidth voting like >>>>> ICC BW votings etc. >>>>> >>>>> So, add pre_link_speed_change() & post_link_speed_change() op to call >>>>> before & after the link re-train. There is no explicit locking mechanisms >>>>> as these are called by a single client Endpoint driver. >>>>> >>>>> In case of PCIe switch, if there is a request to change target speed for a >>>>> downstream port then no need to call these function ops as these are >>>>> outside the scope of the controller drivers. >>>> >>>>> +++ b/include/linux/pci.h >>>>> @@ -599,6 +599,24 @@ struct pci_host_bridge { >>>>>       void (*release_fn)(struct pci_host_bridge *); >>>>>       int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); >>>>>       void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); >>>>> +    /* >>>>> +     * Callback to the host bridge drivers to update ICC BW votes, clock >>>>> +     * frequencies etc.. for the link re-train to come up in targeted speed. >>>>> +     * These are intended to be called by devices directly attached to the >>>>> +     * Root Port. These are called by a single client Endpoint driver, so >>>>> +     * there is no need for explicit locking mechanisms. >>>>> +     */ >>>>> +    int (*pre_link_speed_change)(struct pci_host_bridge *bridge, >>>>> +                     struct pci_dev *dev, int speed); >>>>> +    /* >>>>> +     * Callback to the host bridge drivers to adjust ICC BW votes, clock >>>>> +     * frequencies etc.. to the updated speed after link re-train. These >>>>> +     * are intended to be called by devices directly attached to the >>>>> +     * Root Port. These are called by a single client Endpoint driver, >>>>> +     * so there is no need for explicit locking mechanisms. >>>> >>>> No need to repeat the entire comment.  s/.././ >>>> >>>> These pointers feel awfully specific for being in struct >>>> pci_host_bridge, since we only need them for a questionable QCOM >>>> controller.  I think this needs to be pushed down into qcom somehow as >>>> some kind of quirk. >>>> >>> Currently these are needed by QCOM controllers, but it may also needed >>> by other controllers may also need these for updating ICC votes, any >>> system level votes, clock frequencies etc. >>> QCOM controllers is also doing one extra step in these functions to >>> disable and enable ASPM only as it cannot link speed change support >>> with ASPM enabled. >>> >> Bjorn, can you check this. >> >> For QCOM devices we need to update the RPMh vote i.e a power source >> votes for the link to come up in required speed. and also we need >> to update interconnect votes also. This will be applicable for >> other vendors also. >> >> If this is not correct place I can add them in the pci_ops. > Bjorn, > > Can you please comment on this. > > Is this fine to move these to the pci_ops of the bridge. > Again these are not specific to QCOM, any controller driver which > needs to change their clock rates, ICC bw votes etc needs to have > these. Do you even need to set the OPP explicitly? The global irq handler already does so on linkup, and you seem to toggle the link state in the newly introduced helpers Now not all DTs currently have a global interrupt, but that's a mass fixup to be done anyway.. Konrad