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[192.35.156.11]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498d40a7esm5035005ad.70.2025.10.24.17.41.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Oct 2025 17:41:19 -0700 (PDT) Message-ID: <39732bf6-dd6f-b808-7c10-b3faa4d46489@oss.qualcomm.com> Date: Fri, 24 Oct 2025 17:41:18 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v5 07/10] phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings Content-Language: en-US From: Wesley Cheng To: Abel Vesa Cc: krzk+dt@kernel.org, conor+dt@kernel.org, konrad.dybcio@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251006222002.2182777-1-wesley.cheng@oss.qualcomm.com> <20251006222002.2182777-8-wesley.cheng@oss.qualcomm.com> <9d3dd1cf-4969-3dcb-18dc-59cfb68033f7@oss.qualcomm.com> In-Reply-To: <9d3dd1cf-4969-3dcb-18dc-59cfb68033f7@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAxOCBTYWx0ZWRfX0vCaTHvHPJWS 4WYWShGw54cf3uFNwqLHv2V4myn/GaBPzi/T0OQOBVTSh/t3qjzqiZ6qZomAtfnxSDWetDtzhtF S9KSNhGPo5V8LJHoATwfvfNkVFOt5LPLulQYUI/BqBwALfWjAGiEVP+mN9BJ10w9SVY2roGEeZp Pz+q049E7oZLKwZKmWR9JaqU1110gITInTOUe3KiwXbGJDJxTx4xcqAvhhV6RDmYoxXO4DgVd6P HQCp6TZIPvP5eMrcMUyW1eD1pQoKz6xOMFrE/PbYJLffUaDLUgnJ6eKQb6qFmazFgAHoDvQaosM plXrE6Y3IkaN0CD13dxw0VrM+gZPZpYL0bTAawg4ApxYhanhTeqdN19guxO/JdIlTf2n7XcrGvO mMOVukANILcnzYu6MaBR4zt65CpLbA== X-Authority-Analysis: v=2.4 cv=G4UR0tk5 c=1 sm=1 tr=0 ts=68fc1cb2 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZdW6uxA9NKXbfdqeeS2OGA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RNL1vAbd1nz3C39zmhQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: ijMgUYcblKGBlAwq-CfVE5yZyM-OjULO X-Proofpoint-ORIG-GUID: ijMgUYcblKGBlAwq-CfVE5yZyM-OjULO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-24_05,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180018 On 10/24/2025 5:02 PM, Wesley Cheng wrote: > > > On 10/24/2025 3:04 AM, Abel Vesa wrote: >> On 25-10-06 15:19:59, Wesley Cheng wrote: >>> For SuperSpeed USB to work properly, there is a set of HW settings that >>> need to be programmed into the USB blocks within the QMP PHY.  Ensure >>> that >>> these settings follow the latest settings mentioned in the HW >>> programming >>> guide.  The QMP USB PHY on Glymur is a USB43 based PHY that will have >>> some >>> new ways to define certain registers, such as the replacement of TXA/RXA >>> and TXB/RXB register sets.  This was replaced with the LALB register >>> set. >>> >>> There are also some PHY init updates to modify the PCS MISC register >>> space. >>> Without these, the QMP PHY PLL locking fails. >>> >>> Reviewed-by: Dmitry Baryshkov >>> Signed-off-by: Wesley Cheng >>> --- >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c     | 314 ++++++++- >>>   .../phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h    |  17 + >>>   .../phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h   |  12 + >>>   .../qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h   | 639 ++++++++++++++++++ >>>   .../phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h  |  33 + >>>   .../phy-qcom-qmp-usb43-qserdes-com-v8.h       | 224 ++++++ >>>   drivers/phy/qualcomm/phy-qcom-qmp.h           |   2 + >>>   7 files changed, 1240 insertions(+), 1 deletion(-) >>>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h >>>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h >>>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h >>>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h >>>   create mode 100644 >>> drivers/phy/qualcomm/phy-qcom-qmp-usb43-qserdes-com-v8.h >>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >>> b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >>> index 1caa1fb6a8c7..8216820e388f 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >> >> [...] >> >>> +static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = { >>> +    .offsets        = &qmp_combo_usb43dp_offsets_v8, >>> + >>> +    .serdes_tbl        = glymur_usb43dp_serdes_tbl, >>> +    .serdes_tbl_num        = ARRAY_SIZE(glymur_usb43dp_serdes_tbl), >>> +    .tx_tbl            = glymur_usb43dp_lalb_tbl, >>> +    .tx_tbl_num        = ARRAY_SIZE(glymur_usb43dp_lalb_tbl), >>> +    .pcs_tbl        = glymur_usb43dp_pcs_tbl, >>> +    .pcs_tbl_num        = ARRAY_SIZE(glymur_usb43dp_pcs_tbl), >>> +    .pcs_usb_tbl        = glymur_usb43dp_pcs_usb_tbl, >>> +    .pcs_usb_tbl_num    = ARRAY_SIZE(glymur_usb43dp_pcs_usb_tbl), >>> +    .pcs_misc_tbl        = glymur_usb43dp_pcs_misc_tbl, >>> +    .pcs_misc_tbl_num    = ARRAY_SIZE(glymur_usb43dp_pcs_misc_tbl), >>> + >>> +    .dp_serdes_tbl        = qmp_v6_n4_dp_serdes_tbl, >>> +    .dp_serdes_tbl_num    = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl), >>> +    .dp_tx_tbl        = qmp_v6_n4_dp_tx_tbl, >>> +    .dp_tx_tbl_num        = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl), >>> + >>> +    .serdes_tbl_rbr        = qmp_v6_n4_dp_serdes_tbl_rbr, >>> +    .serdes_tbl_rbr_num    = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr), >>> +    .serdes_tbl_hbr        = qmp_v6_n4_dp_serdes_tbl_hbr, >>> +    .serdes_tbl_hbr_num    = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr), >>> +    .serdes_tbl_hbr2    = qmp_v6_n4_dp_serdes_tbl_hbr2, >>> +    .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2), >>> +    .serdes_tbl_hbr3    = qmp_v6_n4_dp_serdes_tbl_hbr3, >>> +    .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3), >>> + >>> +    .swing_hbr_rbr        = &qmp_dp_v6_voltage_swing_hbr_rbr, >>> +    .pre_emphasis_hbr_rbr    = &qmp_dp_v6_pre_emphasis_hbr_rbr, >>> +    .swing_hbr3_hbr2    = &qmp_dp_v5_voltage_swing_hbr3_hbr2, >>> +    .pre_emphasis_hbr3_hbr2    = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, >>> + >>> +    .dp_aux_init        = qmp_v4_dp_aux_init, >>> +    .configure_dp_tx    = qmp_v4_configure_dp_tx, >>> +    .configure_dp_phy    = qmp_v4_configure_dp_phy, >>> +    .calibrate_dp_phy    = qmp_v4_calibrate_dp_phy, >> >> So I see you are adding the DP related config here as well, but it is >> definitely not compatible with v6 N4. I'm assyuming you picked v6 N4 >> as a default >> just to allow the USB part work for now, right ? >> >> I don't suppose we can drop the DP related config from this patch and >> still have the USB part working, right? >> >> Otherwise, we need to mention the fact that even though the DP part >> is also being added, it is broken. > > Hi Abel, > > That is correct.  Without these defined, the USB path won't work, and > we'll need to supplement this if we wanted to add DP support.  Hence, > why I didn't add any mention of DP altmode in the commit text.  I can > clarify that we added DP placeholders if that makes it more clear in the > commit text. > Hi Abel, I take that back...I went back and reviewed the QMP combo driver again, and gave it a try w/o any of the DP init tables. SS USB is working fine. I will update the patch to remove the DP entries. Thanks for catching this. Thanks Wesley Cheng