From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932461AbcIMTMF (ORCPT ); Tue, 13 Sep 2016 15:12:05 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:35742 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932415AbcIMTMC (ORCPT ); Tue, 13 Sep 2016 15:12:02 -0400 Subject: Re: [PATCH 2/2] usb: dwc3: Added a property to set GFLADJ register To: Rob Herring , John Youn References: <649b249e86e901b5bd2cf4cbe9db96d04a45f30d.1472764828.git.johnyoun@synopsys.com> <20160912153018.GA14561@rob-hp-laptop> CC: Felipe Balbi , Greg Kroah-Hartman , "linux-usb@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Mark Rutland , "Thinh Nguyen" From: John Youn Message-ID: <39809403-0b2b-09d9-452d-9689505ecff7@synopsys.com> Date: Tue, 13 Sep 2016 12:12:00 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <20160912153018.GA14561@rob-hp-laptop> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.9.140.13] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/12/2016 8:30 AM, Rob Herring wrote: > On Thu, Sep 01, 2016 at 02:32:33PM -0700, John Youn wrote: >> From: Thinh Nguyen >> >> Added gfladj variable to control the core behavior with respect to >> SOF, ITP, and frame timer functionality. >> >> Currently there is dwc->fladj that holds a single field in GFLADJ >> register (GFLADJ.GFLADJ_30MHZ). A new variable gfladj is added to >> dwc structure to allow setting of the entire GFLADJ register. If >> dwc->gfladj is set, then it has a higher priority than dwc->fladj >> when writing to the GFLADJ register. > > I'm not a fan of magic register values for DT properties. > Sure. Felipe gave the same feedback. We'll fix it. > How many fields in this register that you will ever need to touch? > >> Synopsys HW setup (HAPS DX and phy board) requires a preset to this >> register to improve interoperablitity. For example, the value for >> GFLADJ_REFCLK_LPM_SEL should be set to 0 with ref_clk period of 50. > > This sounds like it should be handled in the driver. Is it a simple, > constant correlation of ref_clk period to this value? I don't know. I'll look into it. Regards, John