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[46.122.100.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49949fc2da2sm3363735e9.3.2026.08.03.09.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 09:11:42 -0700 (PDT) From: Jernej Skrabec To: wens@kernel.org Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, samuel@sholland.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 13/13] drm/sun4i: Align VI buffer addresses for subsampled formats Date: Mon, 3 Aug 2026 18:10:51 +0200 Message-ID: <3980ea1aeb3f7fe8b4700e36560deeba3d050664.1785772659.git.jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This is a partial revert of commit 79ac1c945ab8 ("drm/sun4i: layers: Use drm_fb_dma_get_gem_addr() to get display memory"). Chroma must start at the beginning of a subsampling block, for example chroma start address for NV12 must be aligned to 2 pixels. drm_fb_dma_get_gem_addr() offsets luma by the exact source coordinates and chroma by the coordinates divided by the subsampling factor, so for odd offsets both planes no longer describe the same pixel, which the Display Engine scaler can't handle. Align source coordinates down for all planes instead. Remaining shift of one pixel is already compensated with scaler phase shift in sun8i_vi_layer_update_coord(). Fixes: 79ac1c945ab8 ("drm/sun4i: layers: Use drm_fb_dma_get_gem_addr() to get display memory") Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 09f668c8af24..ad036cb9d88e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -197,15 +197,31 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer, struct drm_plane_state *state = plane->state; struct drm_framebuffer *fb = state->fb; const struct drm_format_info *format = fb->format; + struct drm_gem_dma_object *gem; + u32 dx, dy, src_x, src_y; dma_addr_t dma_addr; u32 ch_base; int i; ch_base = sun8i_channel_base(layer); + /* Adjust x and y to be divisible by subsampling factor */ + src_x = (state->src.x1 >> 16) & ~(format->hsub - 1); + src_y = (state->src.y1 >> 16) & ~(format->vsub - 1); + for (i = 0; i < format->num_planes; i++) { - /* Get the start of the displayed memory */ - dma_addr = drm_fb_dma_get_gem_addr(fb, state, i); + gem = drm_fb_dma_get_gem_obj(fb, i); + dma_addr = gem->dma_addr + fb->offsets[i]; + + dx = src_x; + dy = src_y; + if (i > 0) { + dx /= format->hsub; + dy /= format->vsub; + } + + dma_addr += dx * format->cpp[i]; + dma_addr += dy * fb->pitches[i]; /* Set the line width */ DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n", -- 2.43.0