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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485187ced3bsm11058185e9.8.2026.03.03.16.02.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2026 16:02:20 -0800 (PST) Message-ID: <39828202-9f48-44f9-9f28-574f141e2ee9@linaro.org> Date: Wed, 4 Mar 2026 00:02:18 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Vijay Kumar Tumati , Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260226-x1e-csi2-phy-v3-0-11e608759410@linaro.org> <20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org> <4pFL6wOeTKUt-Zq4YbjqJdacMgUIPSYJD-4-5DcIMEZ1sM7JsNFYcSv1bd7ZRVOklTsmkEfxM2b6tTflmiECNQ==@protonmail.internalid> <03b44922-72d5-465b-96e1-97a19655e97d@kernel.org> <4440a3a8-7281-4bea-bb84-7a9d19ef7ce9@oss.qualcomm.com> <2a1155bd-7dc5-4ed8-b1eb-ddfa483c75ca@oss.qualcomm.com> <4fea7117-ebd3-4279-9973-3ac4f2a78835@linaro.org> <8e7c2036-74de-4f21-8269-8e2b24323753@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <8e7c2036-74de-4f21-8269-8e2b24323753@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 03/03/2026 23:50, Vijay Kumar Tumati wrote: > Sure, I was just giving an example. I haven't looked a lot into the > IPCAT / clock corners of this target particularly. Someone needs to > check the clock plan, I mean, feel free. understand which PHYs require which power domains > and add that in the following OPP table and as for scaling you can use > the same RPMH levels for all those power domains. Btw, if you had > defined the below OPP table for TOP GDSC, I think that is wrong. It only > has two perf states (on and off) and doesn't need OPP scaling. If you > look at the Iris driver, they link only the mxc and mmcx power domains > to the OPP table using 'PD_FLAG_REQUIRED_OPP, not the GDSCs. >> >> +    csiphy_opp_table: opp-table-csiphy { >> +        compatible = "operating-points-v2"; >> + >> +        opp-300000000 { >> +            opp-hz = /bits/ 64 <300000000>; >> +            required-opps = <&rpmhpd_opp_low_svs_d1>; >> +        }; >> + >> +        opp-400000000 { >> +            opp-hz = /bits/ 64 <400000000>; >> +            required-opps = <&rpmhpd_opp_low_svs>; >> +        }; >> + >> +        opp-480000000 { >> +            opp-hz = /bits/ 64 <480000000>; >> +            required-opps = <&rpmhpd_opp_low_svs>; >> +        }; >> +    }; >> >> --- >> bod Yes, we should scale the MX*, that's incorrect. csiphy_mxc_opp_table: opp-table-csiphy-mxc { compatible = "operating-points-v2"; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_low_svs_d1>, <&rpmhpd_opp_low_svs_d1>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; required-opps = <&rpmhpd_opp_low_svs>, <&rpmhpd_opp_low_svs>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_low_svs>, <&rpmhpd_opp_low_svs>; }; }; csiphy_mxa_opp_table: opp-table-csiphy-mxa { compatible = "operating-points-v2"; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_low_svs_d1>, <&rpmhpd_opp_low_svs_d1>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; required-opps = <&rpmhpd_opp_low_svs>, <&rpmhpd_opp_low_svs>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; required-opps = <&rpmhpd_opp_low_svs>, <&rpmhpd_opp_low_svs>; }; }; csiphy0: phy@ace4000 { power-domains = <&rpmhpd RPMHPD_MXC>, <&rpmhpd RPMHPD_MMCX>; operating-points-v2 = <&csiphy_mxc_opp_table>; ... }; csiphy4: phy@acec000 { power-domains = <&rpmhpd RPMHPD_MXA>, <&rpmhpd RPMHPD_MMCX>; operating-points-v2 = <&csiphy_mxa_opp_table>; ... }; --- bod